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| mx25l51245g p/n: pm2006 mx25l51245g datasheet preliminary
2 contents 1. features .............................................................................................................................................................. 4 2. general description ..................................................................................................................................... 6 table 1. read performance comparison .................................................................................................... 6 3. pin configurations ......................................................................................................................................... 7 4. pin description .................................................................................................................................................. 7 5. block diagram ................................................................................................................................................... 8 6. data protection ................................................................................................................................................ 9 table 2. protected area sizes ....................... ............................................................................................ 10 table 3. 4k-bit secured otp defnition ....................... ............................................................................. 11 7. memory organization ........................................................................................................................................... 12 table 4. memory organization .................................................................................................................. 12 8. device operation ............................................................................................................................................ 13 8-1. 256mb address protocol ... ....................................................................................................................... 15 8-2. quad peripheral interface (qpi) read mode .......................................................................................... 18 9. command description ................................................................................................................................... 19 table 5. command set .............................................................................................................................. 19 9-1. w rite enable (wren) ... ........................................................................................................................... 24 9-2. w rite disable (wrdi) ............................................................................................................................... 25 9-3. read identifcation (rdid) ... .................................................................................................................... 26 9-4. release from deep power-down (rdp), read electronic signature (res) ... ........................................ 27 9-5. read electronic manufacturer id & device id (rems) ........................................................................... 29 9-6. qpi id read (qpiid) ............................................................................................................................... 30 table 6. id defnitions .............................................................................................................................. 30 9-7. read status register (rdsr) ................................................................................................................. 31 9-8. read confguration register (rdcr) ... ................................................................................................... 32 9-9. w rite status register (wrsr) ................................................................................................................. 38 table 7. protection modes ......................................................................................................................... 39 9-10. enter 4-byte mode (en4b) ...................................................................................................................... 42 9-11. exit 4-byte mode (ex4b) ......................................................................................................................... 42 9-12. read data bytes (read) ... ..................................................................................................................... 43 9-13. read data bytes at higher speed (f ast_read) ... ............................................................................... 44 9-14. dual output read mode (dread) .......................................................................................................... 45 9-15. 2 x i/o read mode (2read) ................................................................................................................... 46 9-16. quad read mode (qread) ... ................................................................................................................. 47 9-17. 4 x i/o read mode (4read) ................................................................................................................... 48 9-18. fast double transfer rate read (fastdtrd) ....................................................................................... 50 9-19. 2 x i/o double transfer rate read mode (2dtrd) ................................................................................ 51 9-20. 4 x i/o double transfer rate read mode (4dtrd) ................................................................................ 52 9-21. preamble bit ........................................................................................................................................... 54 9-22. 4 byte address command set ... .............................................................................................................. 59 9-23. performance enhance mode ................................................................................................................... 65 9-24. performance enhance mode reset ......................................................................................................... 70 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 3 9-25. burst read ... ............................................................................................................................................ 72 9-26. fast boot .. ............................................................................................................................................... 73 9-27. sector erase (se) .................................................................................................................................... 76 9-28. block erase (be32k) ............................................................................................................................... 77 9-29. block erase (be) ..................................................................................................................................... 78 9-30. chip erase (ce) ....................................................................................................................................... 79 9-31. page program (pp) ................................................................................................................................. 80 9-32. 4 x i/o page program (4pp) ... ................................................................................................................. 82 9-33. deep power-down (dp) ........................................................................................................................... 83 9-34. enter secured otp (enso) .................................................................................................................... 84 9-35. exit secured otp (exso) ... .................................................................................................................... 84 9-36. read security register (rdscur) ......................................................................................................... 84 9-37. w rite security register (wrscur) ......................................................................................................... 84 table 8. security register defnition ......................................................................................................... 85 9-38. w rite protection selection (wpsel) ........................................................................................................ 86 9-39. advanced sector protection ... ................................................................................................................. 88 9-40. program/erase suspend/resume ........................................................................................................... 97 9-41. erase suspend ........................................................................................................................................ 97 9-42. program suspend .................................................................................................................................... 97 9-43. write-resume ... ....................................................................................................................................... 99 9-44. no operation (nop) ................................................................................................................................ 99 9-45. software reset (reset-enable (rsten) and reset (rst)) ................................................................... 99 9-46. read sfdp mode (rdsfdp) ................................................................................................................ 101 table 9. signature and parameter identifcation data values ................................................................ 102 table 10. parameter table (0): jedec flash parameter tables ............................................................ 103 table 11. parameter table (1): macronix flash parameter tables .......................................................... 105 10. reset ................................................................................................................................................................ 107 table 12. reset timing-(power on) ....................... ................................................................................. 107 table 13. reset timing-(other operation) .............................................................................................. 107 11. power-on state ........................................................................................................................................... 108 12. electrical specifications ...................................................................................................................... 109 table 14. absolute maximum ratings .......................................................................................... 109 table 15. capacitance ta = 25c, f = 1.0 mhz .................................................................................. 109 table 16. dc characteristics (temperature = -40 c to 85 c, vcc = 2.7v ~ 3.6v) ..................... 111 table 17. ac characteristics (temperature = -40 c to 85 c, vcc = 2.7v ~ 3.6v) .................... 112 13. operating conditions ............................................................................................................................... 113 table 18. power-up/down voltage and timing ....................... ............................................................... 115 13-1. initial delivery state ..................................................................................................................... 115 14. erase and programming performance ............................................................................................ 116 15. data retention ............................................................................................................................................ 116 16. latch-up characteristics ...................................................................................................................... 116 17. ordering information .............................................................................................................................. 117 18. part name description ............................................................................................................................. 118 19. package information ................................................................................................................................ 119 20. revision history ......................................................................................................................................... 122 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 4 1. features general ? serial peripheral interface compatible -- mode 0 and mode 3 ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? 512mb: 536,870,912 x 1 bit structure or 268,435,456 x 2 bits (two i/o mode) structure or 134,217,728 x 4 bits (four i/o mode) structure ? protocol support - single i/o, dual i/o and quad i/o ? latch-up protected to 100ma from -1v to vcc +1v ? low vcc write inhibit is from 2.3v to 2.5v ? fast read for spi mode - support clock frequency up to 166mhz for all protocols - support fast read, 2read, dread, 4read, qread instructions - support dtr ( double transfer rate) mode - confgurable dummy cycle number for fast read operation ? quad peripheral interface (qpi) available ? equal sectors with 4k byte each, or equal blocks with 32k byte each or equal blocks with 64k byte each - any block can be erased individually ? programming : - 256byte page buf fer - quad input/output page program(4pp) to enhance program performance ? t ypical 100,000 erase/program cycles ? 20 years data retention software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp0-bp3 and t/b status bits defne the size of the area to be protected against program and erase instructions - advanced sector protection function (solid and password protect) ? additional 4k bit security otp - features unique identifer - factory locked identifable, and customer lockable ? command reset ? program/erase suspend and resume operation ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - rems command for 1-byte manufacturer id and 1-byte device id ? support serial flash discoverable parameters (sfdp) mode 3v 512m-bit [x 1/x 2/x 4] cmos mxsmio (serial multi i/o) flash memory mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 5 hardware features ? sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? so/sio1 - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? wp#/sio2 - hardware write protection or serial data input/output for 4 x i/o read mode ? reset#/sio3 - hardware reset pin or serial input & output for 4 x i/o read mode ? p ackage - 16-pin sop (300mil) - 8-land wson (8x6mm) - 24-ball bga (5x5 ball array) - all devices are rohs compliant and halogen-free mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 6 2. general description mx25l51245g is 512mb bits serial flash memory, which is confgured as 67,108,864 x 8 internally. when it is in two or four i/o mode, the structure becomes 268,435,456 bits x 2 or 134,217,728 bits x 4. mx25l51245g feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single i/o mode. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in two i/o read mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits input and data output. when it is in four i/o read mode, the si pin, so pin, wp# and reset# pin become sio0 pin, sio1 pin, sio2 pin and sio3 pin for address/dummy bits input and data output. the mx25l51245g mxsmio ? (serial multi i/o) provides sequential read operation on whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the specifed page or sector/block locations will be executed. progr am command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4k-byte), block (32k-byte), or block (64k-byte), or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please see security features section for more details. when the device is not in operation and cs# is high, it is put in standby mode. the mx25l51245g utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. table 1. read performance comparison numbers of dummy cycles fast read (mhz) dual output fast read (mhz) quad output fast read (mhz) dual io fast read (mhz) quad io fast read (mhz) 4 - - - 84* 70 6 133 133 104 104 84* 8 133* 133* 133* 133 104 10 166 166 166 166 133 note: * mean default status numbers of dummy cycles fast dtr read (mhz) dual i/o dt read (mhz) quad i/o dt read (mhz) 4 - 52* 42 6 66 66 52* 8 66* 66 66 10 83 83 83 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 7 3. pin configurations 4. pin description symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) so/sio1 serial data output (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) sclk clock input wp#/sio2 write protection: connect to gnd or serial data input & output (for 4xi/o read mode) nc/sio3 no connection or serial data input & output (for 4xi/o read mode) reset# hardware reset pin active low vcc + 3v power supply gnd ground nc no connection dnu do not use (it may connect to internal signal inside) 16-pin sop (300mil) 1 2 3 4 5 6 7 8 nc/sio3 vcc reset# nc dnu dnu cs# so/sio1 16 15 14 13 12 11 10 9 sclk si/sio0 nc nc dnu dnu gnd wp#/sio2 8-wson (8x6mm) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc reset#/sio3 sclk si/sio0 note: reset# pin has internal pull up. 24-ball bga (5x5 ball array) reset# vcc wp#/sio2 nc/sio3 nc nc gnd nc si/sio0 nc nc sclk so/sio1 nc nc nc nc nc nc nc nc a b c d e 5 4 3 2 1 cs# nc nc mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 8 5. block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk so/sio1 clock generator state machine mode logic sense amplifier hv generator output buffer cs# wp#/sio2 reset#/sio3 reset pin mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 9 6. data protection during power transition, there may be some false system level signals which result in inadvertent erasure or programming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command sequences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise. ? v alid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? w rite enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic signature command (res), erase/program suspend command, erase/program resume command and softreset command. ? advanced security features: there are some protection and security features which protect content from inadvertent write and hostile access. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 10 i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0 and t/b) bits to allow part of memory to be protected as read only. the protected area defnition is shown as table 2 protected area sizes, the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. - the hardware proteced mode (hpm) use wp#/sio2 to protect the (bp3, bp2, bp1, bp0) bits and status register write protect bit. - in f our i/o and qpi mode, the feature of hpm will be disabled. table 2. protected area sizes protected area sizes (t/b bit = 1) protected area sizes (t/b bit = 0) status bit protect level bp3 bp2 bp1 bp0 512mb 0 0 0 0 0 (none) 0 0 0 1 1 (1 block, protected block 1023rd) 0 0 1 0 2 (2 blocks, protected block 1022nd~1023rd) 0 0 1 1 3 (4 blocks, protected block 1020th~1023rd) 0 1 0 0 4 (8 blocks, protected block 1016th~1023rd) 0 1 0 1 5 (16 blocks, protected block 1008th~1023rd) 0 1 1 0 6 (32 blocks, protected block 992nd~1023rd) 0 1 1 1 7 (64 blocks, protected block 960th~1023rd) 1 0 0 0 8 (128 blocks, protected block 896th~1023rd) 1 0 0 1 9 (256 blocks, protected block 768th~1023rd) 1 0 1 0 10 (512 blocks, protected block 512nd~1023rd) 1 0 1 1 11 (1024 blocks, protected all) 1 1 0 0 12 (1024 blocks, protected all) 1 1 0 1 13 (1024 blocks, protected all) 1 1 1 0 14 (1024 blocks, protected all) 1 1 1 1 15 (1024 blocks, protected all) status bit protect level bp3 bp2 bp1 bp0 512mb 0 0 0 0 0 (none) 0 0 0 1 1 (1 block, protected block 0th) 0 0 1 0 2 (2 blocks, protected block 0th~1th) 0 0 1 1 3 (4 blocks, protected block 0th~3rd) 0 1 0 0 4 (8 blocks, protected block 0th~7th) 0 1 0 1 5 (16 blocks, protected block 0th~15th) 0 1 1 0 6 (32 blocks, protected block 0th~31st) 0 1 1 1 7 (64 blocks, protected block 0th~63rd) 1 0 0 0 8 (128 blocks, protected block 0th~127th) 1 0 0 1 9 (256 blocks, protected block 0th~255th) 1 0 1 0 10 (512 blocks, protected block 0th~511st) 1 0 1 1 11 (1024 blocks, protected all) 1 1 0 0 12 (1024 blocks, protected all) 1 1 0 1 13 (1024 blocks, protected all) 1 1 1 0 14 (1024 blocks, protected all) 1 1 1 1 15 (1024 blocks, protected all) mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 11 ii. additional 4k-bit secured otp for unique identifer: to provide 4k-bit one-time program area for setting device unique serial number - which may be set by factory or system customer. - security register bit 0 ind icates whether the chip is locked by factory or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enter security otp command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exit security otp command. - customer may lock-dow n the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to "table 8. security register defnition" for security register bit defnition and "table 3. 4k-bit secured otp defnition" for address range defnition. - note: once lock-down whatever by factory or customer , it cannot be changed any more. while in 4k-bit secured otp mode, array access is not allowed. table 3. .elw6hfxuhg273hqlwlrq address range size standard factory lock customer lock xxx000~xxx00f 128-bit esn (electrical serial number) determined by customer xxx010~xxx1ff 3968-bit n/a mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 12 table 4. memory organization 7. memory organization block(32k-byte) sector 16383 3fff000h 3ffffffh ? 16376 3ff8000h 3ff8fffh 16375 3ff7000h 3ff7fffh ? 16368 3ff0000h 3ff0fffh 16367 3fef000h 3feffffh ? 16360 3fe8000h 3fe8fffh 16359 3fe7000h 3fe7fffh ? 16352 3fe0000h 3fe0fffh 16351 3fdf000h 3fdffffh ? 16344 3fd8000h 3fd8fffh 16343 3fd7000h 3fd7fffh ? ? ? ? ? ? ? ? ? ? ? ? ? 16336 3fd0000h 3fd0fffh 47 002f000h 002ffffh ? 40 0028000h 0028fffh 39 027000h 0027fffh ? 32 0020000h 0020fffh 31 001f000h 001ffffh ? 24 0018000h 0018fffh 23 0017000h 0017fffh ? 16 0010000h 0010fffh 15 000f000h 000ffffh ? 8 0008000h 0008fffh 7 0007000h 0007fffh ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0000000h 0000fffh 2044 2043 2042 address range 2047 2046 2045 individual block lock/unlock unit:64k-byte individual 16 sectors lock/unlock unit:4k-byte individual block lock/unlock unit:64k-byte individual block lock/unlock unit:64k-byte block(64k-byte) 1021 2 1 0 1023 1022 0 5 4 3 2 1 individual 16 sectors lock/unlock unit:4k-byte mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 13 8. device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. when incorrect command is inputted to this device, this device becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this device should be high-z. 3. when correct command is inputted to this device, this device becomes active mode and keeps the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock (sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as "serial modes supported". 5. for the following instructio ns: rdid, rdsr, rdscur, read/read4b, fast_read/fast_read4b, 2read/2read4b, dread/dread4b, 4read/4read4b, qread/qread4b, rdsfdp, res, rems, qpiid, rddpb, rdspb, rdpass, rdlr, rdear, rdfbr, rdspblk, rdcr, the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se/se4b, be32k/be32k4b, be/be4b, ce, pp/pp4b, 4pp/4pp4b, dp, enso, exso, wrscur, en4b, ex4b, wpsel, gblk, gbulk, spblk, suspend, resume, nop, rsten, rst, eqio, rstqio the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register, program, erase operation, to access the memory array is neglected and not affect the current operation of write status register, program, erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 14 figure 2. serial input timing figure 3. output timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 15 8-1. 256mb address protocol the original 24 bit address protocol of serial flash can only access density size below 128mb. for the memory device of 256mb and above, the 32bit address is requested for access higher memory size. the mx25l51245g provides three different methods to access the whole density: (1) command entry 4-byte address mode: issue enter 4-byte mode command to set up the 4byte bit in confguration register bit. after 4byte bit has been set, the number of address cycle become 32-bit. (2) extended address register (ear): confgure the memory device into four 128mb segments to select which one is active through the ear<0-1>. (3) 4-byte address command set: when issuing 4-byte address command set, 4-byte address (a31-a0) is requested after the instruction code. please note that it is not necessary to issue en4b command before issuing any of 4-byte command set. extended address register the device provides an 8-bit volatile register for extended address register: it identifes the extended address (a31~a24) above 128mb density by using original 3-byte address. extended address register (ear) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a31 a30 a29 a28 a27 a26 a25 a24 for the mx25l51245g the a31 to a26 are don't care. during ear, reading these bits will read as 0. the bit 0 is default as "0". enter 4-byte address mode in 4-byte address mode, all instructions are 32-bits address clock cycles. by using en4b and ex4b to enable and disable the 4-byte address mode. when 4-byte address mode is enabled, the ear<0-1> becomes "don't care" for all instructions requiring 4-byte address. the ear function will be disabled when 4-byte mode is enabled. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 16 when under ear mode, read, program, erase operates in the selected segment by using 3-byte address mode. for the read operation, the whole array data can be continually read out with one command. data output starts from the selected top or bottom 128mb, but it can cross the boundary. when the last byte of the segment is reached, the next byte (in a continuous reading) is the frst byte of the next segment. however, the ear (extended address register) value does not change. the random access reading can only be operated in the selected segment. the chip erase command will erase the whole chip and is not limited by ear selected segment. however, the sector erase ,block erase , program operation are limited in selected segment and will not cross the boundary. figure 4. write ear register (wrear) sequence (spi mode) figure 5. write ear register (wrear) sequence (qpi mode) 21 345678 9 10 11 12 13 14 15 ear in 0 msb sclk si cs# so c5h high-z command mode 3 mode 0 7 6 5 4 3 2 1 0 sclk sio[3:0] cs# 2 3 10 h0 l0 command ear in mode 3 mode 3 mode 0 mode 0 c5h 03ffffffh 02ffffffh 02000000h 03000000h ear<1-0>= 11 ear<1-0>= 10 01ffffffh 00ffffffh 00000000h 01000000h ear<1-0>= 01 ear<1-0>= 00 figure 6. ear operation segments mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 17 figure 7. read ear (rdear) sequence (spi mode) figure 8. read ear (rdear) sequence (qpi mode) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 ear out ear out high-z msb 7 6543210 msb 7 sclk si cs# so c8h mode 3 mode 0 0 1 3 sclk si o[3:0] cs# c8h 2 h0 l0 msb lsb 4 5 7 h0 l0 6 h0 l0 h0 l0 ear out ear out ear out ear out mode 3 mode 0 n mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 18 8-2. quad peripheral interface (qpi) read mode qpi protocol enables user to take full advantage of quad i/o serial flash by providing the quad i/o interface in command cycles, address cycles and as well as data output cycles. enable qpi mode by issuing 35h command, the qpi mode is enable. figure 9. enable qpi sequence mode 3 sclk sio0 cs# mode 0 234567 35h sio[3:1] 0 1 reset qpi (rstqio) to reset the qpi mode, the rstqio (f5h) command is required. after the rstqio command is issued, the device returns from qpi mode (4 i/o interface in command cycles) to spi mode (1 i/o interface in command cycles). note: for eqio and rstqio commands, cs# high width has to follow "write spec" tshsl for next instruction. figure 10. reset qpi mode sclk sio[3:0] cs# f5h mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 19 9. command description table 5. command set read/write array commands command (byte) read (normal read) fast read (fast read data) 2read (2 x i/o read command) dread (1i 2o read) 4read (4 i/o read start from bottom 128mb) qread (1i 4o read) fastdtrd (fast dt read) 2dtrd (dual i/o dt read) mode spi spi spi spi spi/qpi spi spi spi address bytes 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1st byte 03 (hex) 0b (hex) bb (hex) 3b (hex) eb (hex) 6b (hex) 0d (hex) bd (hex) 2nd byte add1 add1 add1 add1 add1 add1 add1 add1 3rd byte add2 add2 add2 add2 add2 add2 add2 add2 4th byte add3 add3 add3 add3 add3 add3 add3 add3 5th byte dummy* dummy* dummy* dummy* dummy* dummy* dummy* data cycles action n bytes read out until cs# goes high n bytes read out until cs# goes high n bytes read out by 2 x i/ o until cs# goes high n bytes read out by dual output until cs# goes high quad i/ o read for bottom 128mb with 6 dummy cycles n bytes read out by quad output until cs# goes high n bytes read out (double transfer rate) until cs# goes high n bytes read out (double transfer rate) by 2xi/ o until cs# goes high command (byte) 4dtrd (quad i/o dt read) pp (page program) 4pp (quad page program) se (sector erase) be 32k (block erase 32kb) be (block erase 64kb) ce (chip erase) mode spi/qpi spi/qpi spi spi/qpi spi/qpi spi/qpi spi/qpi address bytes 3/4 3/4 3/4 3/4 3/4 3/4 0 1st byte ed (hex) 02 (hex) 38 (hex) 20 (hex) 52 (hex) d8 (hex) 60 or c7 (hex) 2nd byte add1 add1 add1 add1 add1 3rd byte add2 add2 add2 add2 add2 4th byte add3 add3 add3 add3 add3 5th byte dummy* data cycles 1-256 1-256 action n bytes read out (double transfer rate) by 4xi/ o until cs# goes high to program the selected page quad input to program the selected page to erase the selected sector to erase the selected 32k block to erase the selected block to erase whole chip * dummy cycle numbers will be different depending on the bit6 & bit 7 (dc0 & dc1) setting in confguration register. notes 2: please note the address cycles above are based on 3-byte address mode. after enter 4-byte address mode by en4b command, the address cycles will be increased to 4byte. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 20 read/write array commands (4 byte address command set) command (byte) 2dtrd4b (dual i/o dt read) 4dtrd4b (quad i/o dt read) pp4b 4pp4b be4b (block erase 64kb) be32k4b (block erase 32kb) se4b (sector erase 4kb) mode spi spi/qpi spi/qpi spi spi/qpi spi/qpi spi/qpi address bytes 4 4 4 4 4 4 4 1st byte be (hex) ee (hex) 12 (hex) 3e (hex) dc (hex) 5c (hex) 21 (hex) 2nd byte add1 add1 add1 add1 add1 add1 add1 3rd byte add2 add2 add2 add2 add2 add2 add2 4th byte add3 add3 add3 add3 add3 add3 add3 5th byte add4 add4 add4 add4 add4 add4 add4 6th byte dummy* dummy* data cycles 1-256 1-256 action n bytes read out (double transfer rate) by 2xi/o until cs# goes high n bytes read out (double transfer rate) by 4xi/o until cs# goes high to program the selected page with 4byte address quad input to program the selected page with 4byte address to erase the selected (64kb) block with 4byte address to erase the selected (32kb) block with 4byte address to erase the selected (4kb) sector with 4byte address command (byte) read4b fast read4b 2read4b dread4b 4read4b qread4b frdtr4b (fast dt read) mode spi spi spi spi spi/qpi spi spi address bytes 4 4 4 4 4 4 4 1st byte 13 (hex) 0c (hex) bc (hex) 3c (hex) ec (hex) 6c (hex) 0e (hex) 2nd byte add1 add1 add1 add1 add1 add1 add1 3rd byte add2 add2 add2 add2 add2 add2 add2 4th byte add3 add3 add3 add3 add3 add3 add3 5th byte add4 add4 add4 add4 add4 add4 add4 6th byte dummy* dummy* dummy* dummy* dummy* dummy* data cycles action read data byte by 4 byte address read data byte by 4 byte address read data byte by 2 x i/o with 4 byte address read data byte by dual output with 4 byte address read data byte by 4 x i/o with 4 byte address read data byte by quad output with 4 byte address n bytes read out (double transfer rate) until cs# goes high mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 21 register/setting commands command (byte) wren (write enable) wrdi (write disable) rdsr (read status register) rdcr (read confguration register) wrsr (write status/ confguration register) rdear (read extended address register) wrear (write extended address register) mode spi/qpi spi/qpi spi/qpi spi/qpi spi/qpi spi/qpi spi/qpi 1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) 01 (hex) c8 (hex) c5 (hex) 2nd byte values 3rd byte values 4th byte 5th byte data cycles 1-2 1 action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to read out the values of the status register to read out the values of the confguration register to write new values of the status/ confguration register read extended address register write extended address register command (byte) wpsel (write protect selection) eqio (enable qpi) rstqio (reset qpi) en4b (enter 4-byte mode) ex4b (exit 4-byte mode) pgm/ers suspend (suspends program/ erase) pgm/ers resume (resumes program/ erase) mode spi/qpi spi qpi spi/qpi spi/qpi spi/qpi spi/qpi 1st byte 68 (hex) 35 (hex) f5 (hex) b7 (hex) e9 (hex) b0 (hex) 30 (hex) 2nd byte 3rd byte 4th byte 5th byte data cycles action to enter and enable individal block protect mode entering the qpi mode exiting the qpi mode to enter 4-byte mode and set 4byte bit as "1" to exit 4-byte mode and clear 4byte bit to be "0" command (byte) dp (deep power down) rdp (release from deep power down) sbl (set burst length) rdfbr (read fast boot register) wrfbr (write fast boot register) esfbr (erase fast boot register) mode spi/qpi spi/qpi spi/qpi spi spi spi 1st byte b9 (hex) ab (hex) c0 (hex) 16(hex) 17(hex) 18(hex) 2nd byte 3rd byte 4th byte 5th byte data cycles 1-4 4 action enters deep power down mode release from deep power down mode to set burst length mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 22 id/security commands command (byte) rdid (read identifc- ation) res (read electronic id) rems (read electronic manufacturer & device id) qpiid (qpi id read) rdsfdp enso (enter secured otp) exso (exit secured otp) mode spi spi/qpi spi qpi spi/qpi spi/qpi spi/qpi address bytes 0 0 0 0 3 0 0 1st byte 9f (hex) ab (hex) 90 (hex) af (hex) 5a (hex) b1 (hex) c1 (hex) 2nd byte x x add1 3rd byte x x add2 4th byte add1 (note 1) add3 5th byte dummy (8) action outputs jedec id: 1-byte manufacturer id & 2-byte device id to read out 1-byte device id output the manufacturer id & device id id in qpi interface read sfdp mode to enter the 4k-bit secured otp mode to exit the 4k-bit secured otp mode command (byte) rdscur (read security register) wrscur (write security register) gblk (gang block lock) gbulk (gang block unlock) wrlr (write lock register) rdlr (read lock register) wrpass (write password register) rdpass (read password register) mode spi/qpi spi/qpi spi/qpi spi/qpi spi spi spi spi address bytes 0 0 0 0 0 0 0 0 1st byte 2b (hex) 2f (hex) 7e (hex) 98 (hex) 2c (hex) 2d (hex) 28 (hex) 27 (hex) 2nd byte 3rd byte 4th byte 5th byte data cycles 2 2 1-8 1-8 action to read value of security register to set the lock-down bit as "1" (once lock-down, cannot be updated) whole chip write protect whole chip unprotect command (byte) passulk (password unlock) wrspb (spb bit program) esspb (all spb bit erase) rdspb (read spb status) spblk (spb lock set) rdspblk (spb lock register read) wrdpb (write dpb register) rddpb (read dpb register) mode spi spi spi spi spi spi spi spi address bytes 0 4 0 4 0 0 4 4 1st byte 29 (hex) e3 (hex) e4 (hex) e2 (hex) a6 (hex) a7 (hex) e1 (hex) e0 (hex) 2nd byte add1 add1 add1 add1 3rd byte add2 add2 add2 add2 4th byte add3 add3 add3 add3 5th byte add4 add4 add4 add4 data cycles 8 1 2 1 1 action mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 23 note 1: the count base is 4-bit for add (2) and dummy(2) because of 2 x i/o. and the msb is on so/sio1 which is different from 1 x i/o condition. note 2: add =00h will output the manufacturer id frst and ad=01h will output device id frst. note 3: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hid - den mode. note 4: before executing rst command, rsten command must be executed. if there is any other command to interfere, the reset operation will be disabled. note 5: the number in parentheses after "add" or "data" stands for how many clock cycles it has. for example, "data(8)" represents there are 8 clock cycles for the data in. please note the number after "add" are based on 3-byte address mode, for 4-byte address mode, which will be increased. reset commands command (byte) nop (no operation) rsten (reset enable) rst (reset memory) mode spi/qpi spi/qpi spi/qpi 1st byte 00 (hex) 66 (hex) 99 (hex) 2nd byte 3rd byte 4th byte 5th byte action mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 24 9-1. write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp/ pp4b, 4pp/4pp4b, se/se4b, be32k/be32k4b, be/be4b, ce, and wrsr, which are intended to change the device content wel bit should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes lowsending wren instruction code cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care in spi mode. figure 11. write enable (wren) sequence (spi mode) 21 34567 high-z 0 06h command sclk si cs# so mode 3 mode 0 figure 12. write enable (wren) sequence (qpi mode) sclk sio[3:0] cs# 06h 0 1 command mode 3 mode 0 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 25 9-2. write disable (wrdi) the write disable (wrdi) instruction is to reset write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes lowsending wrdi instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care in spi mode. the wel bit is reset by following situations: - power-up - reset# pin driven low - wrdi command completion - wrsr command completion - pp/pp4b command completion - 4pp/4pp4b command completion - se/se4b command completion - be32k/be32k4b command completion - be/be4b command completion - ce command completion - pgm/ers suspend command completion - softreset command completion - wrscur command completion - wpsel command completion - gblk command completion - gbulk command completion - wrear command completion - wrlr command completion - wrp ass command completion - p assulk command completion - spblk command completion - wrspb command completion - esspb command completion - wrdpb command completion - wrfbr command completion - esfbr command completion figure 13. write disable (wrdi) sequence (spi mode) 21 34567 high-z 0 mode 3 mode 0 04h command sclk si cs# so mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 26 9-3. read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the macronix manufacturer id and device id are listed as ta ble 6 id defnitions. the sequence of issuing rdid instruction is: cs# goes low sending rdid instruction code24-bits id data out on so to end rdid operation can drive cs# to high at any time during data out. while program/erase operation is in progress, it will not decode the rdid instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. figure 15. read identifcation (rdid) sequence (spi mode only) 21 3456789 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9fh mode 3 mode 0 14 15 10 13 figure 14. write disable (wrdi) sequence (qpi mode) sclk sio[3:0] cs# 04h 0 1 command mode 3 mode 0 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 27 9-4. release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is completed by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in table 17 ac characteristics. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. the rdp instruction is only for releasing from deep power down mode. reset# pin goes low will release the flash from deep power down mode. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table 6 id defnitions. this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeatedly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. figure 16. read electronic signature (res) sequence (spi mode) 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 2 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so abh command mode 3 mode 0 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 28 sclk sio[3:0] cs# mode 0 mode 3 msb lsb data out data in h0xxxxxx l0 deep power-down mode stand-by mode 0 abh 1 2 3 4 6 7 5 3 dummy bytes command figure 17. read electronic signature (res) sequence (qpi mode) figure 18. release from deep power-down (rdp) sequence (spi mode) 21 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so abh command mode 3 mode 0 figure 19. release from deep power-down (rdp) sequence (qpi mode) sclk sio[3:0] cs# abh 0 1 t res1 deep power-down mode stand-by mode command mode 3 mode 0 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 29 9-5. read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specifc device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for macronix (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst. the device id values are listed in table 6 of id defnitions. if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. notes: (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst. figure 20. read electronic manufacturer & device id (rems) sequence (spi mode only) 15 14 13 3 2 1 0 21 345678 9 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 76543 2 0 1 35 31302928 sclk si cs# so sclk si cs# so 90h high-z command mode 3 mode 0 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 30 9-6. qpi id read (qpiid) user can execute this qpiid read instruction to identify the device id and manufacturer id. the sequence of issue qpiid instruction is cs# goes lowsending qpi id instructiondata out on socs# goes high. most signifcant bit (msb) frst. after the command cycle, the device will immediately output data on the falling edge of sclk. the manufacturer id, memory type, and device id data byte will be output continuously , until the cs# goes high. table 6. id defnitions command type mx25l51245g rdid 9fh manufactory id memory type memory density c2 20 1a res abh electronic id 19 rems 90h manufactory id device id c2 19 qpiid afh manufactory id memory type memory density c2 20 1a mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 31 9-7. read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition). it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. figure 21. read status register (rdsr) sequence (spi mode) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05h mode 3 mode 0 figure 22. read status register (rdsr) sequence (qpi mode) 0 1 3 sclk si o[3:0] cs# 05h 2 h0 l0 msb lsb 4 5 7 h0 l0 6 h0 l0 h0 l0 sta tus byte status byte status byte status byte mode 3 mode 0 n mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 32 9-8. read confguration register (rdcr) the rdcr instruction is for reading confguration register bits. the read confguration register can be read at any time (even in program/erase/write confguration register condition). it is recommended to check the write in progress (wip) bit before sending a new instruction when a prog ram, erase, or write confguration register operation is in progress. the sequence of issuing rdcr instruction is: cs# goes low sending rdcr instruction code confguration register data out on so. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. figure 23. read confguration register (rdcr) sequence (spi mode) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 configuration register out high-z msb 7 6543210 configuration register out msb 7 sclk si cs# so 15h mode 3 mode 0 figure 24. read confguration register (rdcr) sequence (qpi mode) 0 1 3 sclk si o[3:0] cs# 15h 2 h0 l0 msb lsb 4 5 7 h0 l0 6 h0 l0 h0 l0 mode 3 mode 0 config. byte config. byte config. byte config. byte n mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 33 wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command read array data (same add ress of pgm/ers) program /er ase su ccessfully yes yes program /erase fail no start verify ok? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wel=1? no * issue rdsr to check bp[3:0]. * if wpsel = 1, issue rdspb and rddpb to ch eck the block stat us. rdsr command read w el=0, bp[3:0] , q e, and srwd data figure 25. program/erase fow with read array data for user to check if program/erase operation is fnished or not, rdsr instruction fow are shown as follows: mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 34 figure 26. program/erase fow without read array data (read p_fail/e_fail fag) wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command rdscur command program /er ase su ccessfully yes no program /erase fail yes start p_fail/e_fail =1 ? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wel=1? no * issue rdsr to check bp[3:0]. * if wpsel = 1, issue rdspb and rddpb to ch eck the block stat us. rdsr command read w el=0, bp[3:0] , q e, and srwd data mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 35 status register note 1: see the table 2 "protected area size". bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1=quad enable 0=not quad enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit status register the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. the program/erase command will be ignored if it is applied to a protected memory area. to ensure both wip bit & wel bit are both set to 0 and available for next program/erase/operations, wip bit needs to be confrm to be 0 before polling wel bit. after wip bit confrmed, wel bit needs to be confrm to be 0. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area (as defned in table 2 ) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase 32kb (be32k), block erase (be) and chip erase (ce) instructions (only if block protect bits (bp3:bp0) set to 0, the ce instruction can be executed). the bp3, bp2, bp1, bp0 bits are "0" as default. which is un-protected. qe bit. the quad enable (qe) bit, non-volatile bit, while it is "0" (factory default), it performs non-quad and wp#, reset# are enable. while qe is "1", it performs quad i/o mode and wp#, reset# are disabled. in the other word, if the system goes into four i/o mode (qe=1), the feature of hpm and reset will be disabled. srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protection (wp#/sio2) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp#/sio2 pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only. the srwd bit defaults to be "0". mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 36 confguration register the confguration register is able to change the default status of flash memory. flash memory will be confgured after the cr bit is set. ods bit the output driver strength (ods2, ods1, ods0) bits are volatile bits, which indicate the output driver level (as defned in output driver strength table ) of the device. the output driver strength is defaulted as 30 ohms when delivered from factory. to write the ods bits requires the write status register (wrsr) instruction to be executed. tb bit the top/bottom (tb) bit is a non-volatile otp bit. the top/bottom (tb) bit is used to confgure the block protect area by bp bit (bp3, bp2, bp1, bp0), starting from top or bottom of the memory array. the tb bit is defaulted as 0, which means top area protect. when it is set as 1, the protect area will change to bottom area of the memory device. to write the tb bits requires the write status register (wrsr) instruction to be executed. pbe bit the preamble bit enable (pbe) bit is a volatile bit. it is used to enable or disable the preamble bit data pattern output on dummy cycles. the pbe bit is defaulted as 0, which means preamble bit is disabled. when it is set as 1, the preamble bit will be enabled, and inputted into dummy cycles. to write the pbe bits requires the write status register (wrsr) instruction to be executed. 4byte indicator bit by writing en4b instruction, the 4byte bit may be set as "1" to access the address length of 32-bit for memory area of higher density (large than 128mb). the default state is "0" as the 24-bit address mode. the 4byte bit may be cleared by power-off or writing ex4b instruction to reset the state to be "0". confguration register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dc1 (dummy cycle 1) dc0 (dummy cycle 0) 4 byte pbe (preamble bit enable) tb (top/bottom selected) ods 2 (output driver strength) ods 1 (output driver strength) ods 0 (output driver strength) (note 2) (note 2) 0=3-byte address mode 1=4-byte address mode (default=0) 0=disable 1=enable 0=top area protect 1=bottom area protect (default=0) (note 1) (note 1) (note 1) volatile bit volatile bit volatile bit volatile bit otp volatile bit volatile bit volatile bit note 1: see 2xwsxw'ulhu6wuhqjwk7deoh note 2: see 'xpp&fohdqg)uhtxhqf7deoh0] mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 37 dummy cycle and frequency table (mhz) output driver strength table ods2 ods1 ods0 description note 0 0 0 reserved impedance at vcc/2 0 0 1 90 ohms 0 1 0 60 ohms 0 1 1 45 ohms 1 0 0 reserved 1 0 1 20 ohms 1 1 0 15 ohms 1 1 1 30 ohms (default) dc[1:0] numbers of dummy clock cycles fast read dual output fast read quad output fast read fast dtr read 00 (default) 8 133 133 133 66 01 6 133 133 104 66 10 8 133 133 133 66 11 10 166 166 166 83 dc[1:0] numbers of dummy clock cycles dual io fast read dual i/o dtr read 00 (default) 4 84 52 01 6 104 66 10 8 133 66 11 10 166 83 dc[1:0] numbers of dummy clock cycles quad io fast read quad i/o dtr read 00 (default) 6 84 52 01 4 70 42 10 8 104 66 11 10 133 83 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 38 note : the cs# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command. figure 27. write status register (wrsr) sequence (spi mode) 21 345678 9 10 11 12 13 14 15 status register in configuration register in 0 msb sclk si cs# so 01h high-z command mode 3 mode 0 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 figure 28. write status register (wrsr) sequence (qpi mode) sclk sio[3:0] cs# 2 3 5 10 4 h0 l0 h1 l1 command sr in cr in mode 3 mode 3 mode 0 mode 0 01h 9-9. write status register (wrsr) the wrsr instruction is for changing the values of status register bits and confguration register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to defne the protected area of memory (as shown in table 2 ). the wrsr also can set or reset the quad enable (qe) bit and set or reset the status register write disable (srwd) bit in accordance with write protection (wp#/ sio2) pin signal, but has no effect on bit1(wel) and bit0 (wip) of the status register. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on sics# goes high. the cs# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 39 table 7. protection modes note: 1. as defned by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in table 2 . mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp3 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. software protected mode (spm): - when srwd bit=0, no matter wp#/sio2 is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0 and t/b bit, is at software protected mode (spm). - when srwd bit=1 and wp#/sio2 is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0 and t/b bit, is at software protected mode (spm) note: if srwd bit=1 but wp#/sio2 is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when srwd bit=1, and then wp#/sio2 is low (or wp#/sio2 is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3, bp2, bp1, bp0 and t/b bit and hardware protected mode by the wp#/sio2 to against data modifcation. note: to exit the hardware protected mode requires wp#/sio2 driving high once the hardware protected mode is entered. if the wp#/sio2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3, bp2, bp1, bp0 and t/b bit. if the system enter qpi or set qe=1, the feature of hpm will be disabled. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 40 figure 29. wrsr fow wr en co mm and wr sr co mm and write status register data rdsr command wrsr successfully yes yes wrsr fail no start verify ok? wip=0? no rds r command yes wel=1? no rds r command read w el=0, bp[3:0] , q e, and srwd data mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 41 figure 30. wp# setup timing and hold timing during wrsr when srwd=1 high-z 01h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so note: wp# must be kept high until the embedded operation fnish. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 42 9-10. enter 4-byte mode (en4b) the en4b instruction enables accessing the address length of 32-bit for the memory area of higher density (larger than 128mb). the device default is in 24-bit address mode; after sending out the en4b instruction, the bit5 (4byte bit) of security register will be automatically set to "1" to indicate the 4-byte address mode has been enabled. once the 4-byte address mode is enabled, the address length becomes 32-bit instead of the default 24-bit. there are three methods to exit the 4-byte mode: writing exit 4-byte mode (ex4b) instruction, reset or power-off. all instructions are accepted normally, and just the address bit is changed from 24-bit to 32-bit. the following command don't support 4bye address: rdsfdp, res and rems. the sequence of issuing en4b instruction is: cs# goes low sending en4b instruction to enter 4-byte mode( automatically set 4byte bit as "1") cs# goes high. 9-11. exit 4-byte mode (ex4b) the ex4b instruction is executed to exit the 4-byte address mode and return to the default 3-bytes address mode. after sending out the ex4b instruction, the bit5 (4byte bit) of confguration register will be cleared to be "0" to indicate the exit of the 4-byte address mode. once exiting the 4-byte address mode, the address length will return to 24-bit. the sequence of issuing ex4b instruction is: cs# goes low sending ex4b instruction to exit 4-byte mode (automatically clear the 4byte bit to be "0") cs# goes high. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 43 9-12. read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to defne ear bit. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. the sequence of issuing read instruction is: cs# goes lowsending read instruction code 3-byte or 4-byte address on si data out on soto end read operation can use cs# to high at any time during data out. figure 31. read data bytes (read) sequence (spi mode only) sclk si cs# so 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 7654 3 1 7 0 data out 1 0 msb msb 2 39 data out 2 03h high-z command mode 3 mode 0 24-bit address (note) note: please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 44 9-13. read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to defne ear bit. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. read on spi mode the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3-byte or 4-byte address on si 8 dummy cycles (default) data out on so to end fast_ read operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status register current cycle. figure 32. read at higher speed (fast_read) sequence (spi mode) 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 configurable dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 0bh command mode 3 mode 0 24-bit address (note) note: please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 45 9-14. dual output read mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maximum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruction. the address counter rolls over to 0 when the highest address has been reached. once writing dread instruction, the following data out will perform as 2-bit instead of previous 1-bit. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to defne ear bit. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. the sequence of issuing dread instruction is: cs# goes low sending dread instruction 3-byte or 4-byte address on sio0 8 dummy cycles (default) on sio0 data out interleave on sio1 & sio0 to end dread operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, dread instruction is rejected without any impact on the program/erase/write status register current cycle. figure 33. dual read mode sequence high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 30 31 32 39 40 41 43 44 45 42 3b d4 d5 d2 d3 d7 d6 d6 d4 d0 d7 d5 d1 command 24 add cycle configurable dummy cycle a23 a22 a1 a0 data out 1 data out 2 notes: 1. please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. 2. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 46 9-15. 2 x i/o read mode (2read) the 2read instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maximum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to defne ear bit. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. the sequence of issuing 2read instruction is: cs# goes low sending 2read instruction 3-byte or 4-byte address interleave on sio1 & sio0 4 dummy cycles (default) on sio1 & sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. figure 34. 2 x i/o read mode sequence (spi mode only) 21 345678 0 sclk si/sio0 so/sio1 cs# 9 10 17 18 19 20 bbh 21 22 23 24 25 26 27 28 29 30 command configurable dummy cycle mode 3 mode 0 mode 3 mode 0 12 add cycles (note) a23 a21 a19 a5 a3 a1 a4 a2 a a22 a20 a18 d6 d4 d7 d5 data out 1 data out 2 d2 d0 d3 d1 d0 d1 d6 d4 d7 d5 d2 d3 notes: 1. please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. 2. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 47 9-16. quad read mode (qread) the qread instruction enable quad throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single qread instruction. the address counter rolls over to 0 when the highest address has been reached. once writing qread instruction, the following data out will perform as 4-bit instead of previous 1-bit. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to defne ear bit. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. the sequence of issuing qread instruction is: cs# goes low sending qread instruction 3-byte or 4-byte address on si 8 dummy cycle (default) data out interleave on so3, so2, so1 & so0 to end qread operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, qread instruction is rejected without any impact on the program/erase/write status register current cycle. high impedance 21 345678 0 sclk sio0 sio1 cs# 29 9 30 31 32 33 38 39 40 41 42 6b high impedance sio2 high impedance sio3 configurable dummy cycles d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d5 d6 d7 a23 a22 a2 a1 a0 command 24 add cycles data out 1 data out 2 data out 3 ? ? ? figure 35. quad read mode sequence notes: 1. please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. 2. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 48 9-17. 4 x i/o read mode (4read) the 4read instruction enable quad throughput of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the 4read instruction. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to defne ear bit. to enter the 4-byte mode, please refer to the enter 4-byte mode (en4b) mode section. 4 x i/o read on spi mode (4read) the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 3-byte or 4-byte address interleave on sio3, sio2, sio1 & sio0 6 dummy cycles (default) data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. 4 x i/o read on qpi mode (4read) the 4read instruction also support on qpi command mode. the sequence of issuing 4read instruction qpi mode is: cs# goes low sending 4read instruction 3-byte or 4-byte address interleave on sio3, sio2, sio1 & sio0 6 dummy cycles (default) data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, 4read instruction is rejected without any impact on the program/erase/write status register current cycle. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 49 figure 36. 4 x i/o read mode sequence (spi mode) 21 345678 0 sclk sio0 sio1 sio2 sio3 cs# 9 1210 11 13 14 ea/ebh p4 p0 p5 p1 p6 p2 p7 p3 15 16 17 18 19 20 21 22 23 24 command configurable dummy cycle (note 3) performance enhance indicator (note 1) mode 3 mode 0 6 add cycles a21 a17 a13 a9 a5 a1 a8 a4 a a20 a16 a12 a23 a19 a15 a11 a7 a3 a10 a6 a2 a22 a18 a14 d4 d0 d5 d1 data out 1 data out 2 data out 3 d4 d0 d5 d1 d4 d0 d5 d1 d6 d2 d7 d3 d6 d2 d7 d3 d6 d2 d7 d3 mode 3 mode 0 notes: 1. hi-impedance is inhibited for the two clock cycles. 2. p7p3, p6p2, p5p1 & p4p0 (t oggling) is inhibited. 3. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. 4. please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. figure 37. 4 x i/o read mode sequence (qpi mode) 3 edom sclk sio[3:0] cs# mode 3 mode 0 mode 0 msb data out ebh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 data in 24-bit address (note) configurable dummy cycle xx a20- a23 a16- a19 a12- a15 a8- a11 a4- a7 a0- a3 x x x x h0 l0 h1 l1 h2 l2 h3 l3 notes: 1. please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. 2. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 50 9-18. fast double transfer rate read (fastdtrd) the fastdtrd instruction is for doubling reading data out, signals are triggered on both rising and falling edge of clock. the address is latched on both rising and falling edge of sclk, and data of each bit shifts out on both rising and falling edge of sclk. the 2-bit address can be latched-in at one clock, and 2-bit data can be read out at one clock, which means one bit at rising edge of clock, the other bit at falling edge of clock. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fastdtrd instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fastdtrd instruction is: cs# goes low sending fastdtrd instruction code (1bit per clock) 3-byte address on si (2-bit per clock) 6-dummy clocks (default) on si data out on so (2-bit per clock) to end fastdtrd operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, fastdtrd instruction is rejected without any impact on the program/erase/write status register current cycle. figure 38. fast dt read (fastdtrd) sequence (spi only) 19 27 28 29 30 31 8 7 0 0dh si/sio0 so/sio1 cs# a23 a22 a1 a0 sclk d7 d6 d5 d4 d3 d2 d1 d7d0 command 12 add cycles configurable dummy cycle data out 1 data out 2 mode 3 mode 0 notes: 1. please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. 2. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 51 9-19. 2 x i/o double transfer rate read mode (2dtrd) the 2dtrd instruction enables double transfer rate throughput on dual i/o of serial flash in read mode. the address (interleave on dual i/o pins) is latched on both rising and falling edge of sclk, and data (interleave on dual i/o pins) shift out on both rising and falling edge of sclk. the 4-bit address can be latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at rising edge of clock, the other two bits at falling edge of clock. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2dtrd instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 2dtrd instruction, the following address/dummy/ data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing 2dtrd instruction is: cs# goes low sending 2dtrd instruction (1-bit per clock) 24- bit address interleave on sio1 & sio0 (4-bit per clock) 6-bit dummy clocks (default) on sio1 & sio0 data out interleave on sio1 & sio0 (4-bit per clock) to end 2dtrd operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, 2dtrd instruction is rejected without any impact on the program/erase/write status register current cycle. figure 39. fast dual i/o dt read (2dtrd) sequence (spi only) 0 7 8 13 14 17 18 19 bdh si/sio0 so/sio1 cs# a22 a20 a23 a21 a2 a0 a3 a1 sclk d6 d4 d2 d0 d6 d4 d2 d0 d6 d7 d5 d3 d1 d7 d5 d3 d1 d7 20 21 data out 1 data out 2 command 6 add cycles configurable dummy cycle mode 3 mode 0 notes: 1. please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address cycles will be increased. 2. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 52 9-20. 4 x i/o double transfer rate read mode (4dtrd) the 4dtrd instruction enables double transfer rate throughput on quad i/o of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the 4dtrd instruction. the address (interleave on 4 i/o pins) is latched on both rising and falling edge of sclk, and data (interleave on 4 i/o pins) shift out on both rising and falling edge of sclk. the 8-bit address can be latched-in at one clock, and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4dtrd instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 4dtrd instruction, the following address/ dummy/data out will perform as 8-bit instead of previous 1-bit. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. while program/erase/write status register cycle is in progress, 4dtrd instruction is rejected without any impact on the program/erase/write status register current cycle. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 53 figure 40. fast quad i/o dt read (4dtrd) sequence (spi mode) edh sio0 sio1 cs# sio2 sio3 sclk p4 p0 d7 d3 d6 d2 d5 d1 d4 d0 d7 d3 d6 d2 d5 d1 d4 d0 d7 d6 d5 d4 performance enhance indicator 0 7 8 9 10 11 16 17 18 a0 a20 a16 a17a21 a18a22 a19a23 a4 a1a5 a2a6 a3 a7 command 3 add cycles p7 p6 p5 p1 p2 p3 configurable dummy cycle mode 3 mode 0 figure 41. fast quad i/o dt read (4dtrd) sequence (qpi mode) configurable dummy cycle edh sio[3:0] cs# sclk p1 p0 h0 l0 h1 l1 h2 performance enhance indicator 0 mode 3 mode 0 1 2 3 4 5 10 11 12 command 3 add cycles a20 | a23 a16 | a19 a12 | a15 a8 | a11 a4 | a7 a0 | a3 notes: 1. hi-impedance is inhibited for this clock cycle. 2. p7p3, p6p2, p5p1 & p4p0 (toggling) will result in entering the performance enhance mode. 3. confguration dummy cycle numbers will be different depending on the bit6 & bit 7 (dc0 & dc1) setting in confguration register. 4. please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. notes: 1. please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. 2. confguration dummy cycle numbers will be different depending on the bit6 & bit 7 (dc0 & dc1) setting in confguration register. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 54 9-21. preamble bit figure 42. sdr 1i/o (10dc) cs# cmd sck si so a0 d7 d6 command cycle address cycle dummy cycle preamble bits 7 6 5 4 3 2 1 0 an figure 43. sdr 1i/o (8dc) cs# cmd sck an a0 2 d4 command cycle address cycle dummy cycle preamble bits 7 6 5 4 3 d5 d7 d6 si so the preamble bit data pattern supports system/memory controller to determine valid window of data output more easily and improve data capture reliability while the fash memory is running in high frequency . preamble bit data pattern can be enabled or disabled by setting the bit4 of confguration register (preamble bit enable bit). once the cr<4> is set, the preamble bit is inputted into dummy cycles. enabling preamble bit will not affect the function of enhance mode bit. in dummy cycles, performance enhance mode bit still operates with the same function. preamble bit will output after performance enhance mode bit. the preamble bit is a fxed 8-bit data pattern (00110100). while dummy cycle number reaches 10, the complete 8 bits will start to output right after the performance enhance mode bit. while dummy cycle is not suffcient of 10 cycles, the rest of the preamble bits will be cut. for example, 8 dummy cycles will cause 6 preamble bits to output, and 6 dummy cycles will cause 4 preamble bits to output. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 55 figure 44. sdr 2i/o (10dc) figure 45. sdr 2i/o (8dc) cs# cmd sck sio0 a0 a(n-1) 7 6 5 4 3 2 1 0 d6 d4 command cycle address cycle dummy cycle toggle bits preamble bits sio1 a1 an 7 6 5 4 3 2 1 0 d7 d5 d2 d0 d3 d1 cs# cmd sck sio0 a0 a(n-1) 7 6 5 4 3 2 d6 d4 command cycle dummy cycle toggle bits sio1 a1 an 7 6 5 4 3 2 d7 d5 d2 d0 d3 d1 address cycle preamble bits mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 56 figure 46. sdr 4i/o (10dc) cs# cmd sck sio0 a0 a(n-3) a(n-2) a(n-1) 7 6 5 4 3 2 1 0 d4 d0 command cycle dummy cycle toggle bits sio1 a1 7 6 5 4 3 2 1 0 d5 d1 sio2 a2 7 6 5 4 3 2 1 0 d6 d2 sio3 a3 an 7 6 5 4 3 2 1 0 d7 d3 address cycle preamble bits figure 47. sdr 4i/o (8dc) cs# cmd sck sio0 a0 a(n-3) a(n-2) a(n-1) 7 6 5 4 3 2 d4 d0 command cycle dummy cycle toggle bits sio1 a1 7 6 5 4 3 2 d5 d1 sio2 a2 7 6 5 4 3 2 d6 d2 sio3 a3 an 7 6 5 4 3 2 d7 d3 address cycle preamble bits mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 57 figure 48. dtr1io (dc=8) cs# d7 d6 d5 d4 d3 d2 d1 d0 sck si so a0a1 an cmd command cycle dummy cycle 7 6 5 4 3 2 1 0 7 6 5 4 address cycle preamble bits figure 49. dtr2io (dc=6) cs# cmd sck sio0 sio1 t oggle bits command cycle a2 a0 7 6 5 4 3 2 1 0 d6 d4 d2 d0 d6 d4 d2 d0 an a3 a1 7 6 5 4 3 2 1 0 d7 d5 d3 d1 d7 d5 d3 d1 dummy cycle a(n-1) address cycle preamble bits mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 58 figure 50. dtr2io (dc=8) lear ning pattern cs# cmd sck sio0 sio1 t oggle bits command cycle address cycle a2 a0 7 6 5 4 3 2 1 0 d6 d4 d2 d0 d6 d4 an a3 a1 7 6 5 4 7 6 5 4 7 6 5 4 3 2 1 0 d7 d5 d3 d1 d7 d5 dummy cycle a(n-1) figure 51. dtr4io (dc=6) cs# cmd sck sio0 sio1 t oggle bits command cycle address cycle a(n-3) a(n-2) a0 7 6 5 4 3 2 1 0 d4 d0 a1 7 6 5 4 3 2 1 0 d5 d1 sio2 a(n-1) a2 7 6 5 4 3 2 1 0 d6 d2 sio3 an a3 7 6 5 4 3 2 1 0 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 dummy cycle lear ning pattern mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 59 9-22. 4 byte address command set the operation of 4-byte address command set was very similar to original 3-byte address command set. the only different is all the 4-byte command set request 4-byte address (a31-a0) followed by instruction code. the command set support 4-byte address including: read4b, fast_read4b, dread4b, 2read4b, qread4b, 4read4b, frdtrd4b, 2dtrd4b, 4dtrd4b, pp4b, 4pp4b, se4b, be32k4b, be4b. please note that it is not necessary to issue en4b command before issuing any of 4-byte command set. figure 52. read data bytes using 4 byte address sequence (read4b) sclk si cs# so 31 21 345678 9 10 36 37 38 39 40 41 42 43 30 29 3210 44 45 46 7654 3 1 7 0 high impedance data out 1 command 32 -bit a dd ress 0 msb 2 47 data out 2 13h msb figure 53. read data bytes at higher speed using 4 byte address sequence (fastread4b) sclk si cs# so sclk si cs# so 31 21 345678 9 10 36 37 38 39 30 29 3210 high impedance command 32 -bit a dd ress 0 40 41 42 44 45 46 47 48 49 50 51 52 53 54 76543 2 0 1 data out 1 configurable 7 6543210 data out 2 7 55 76543 2 0 1 43 0ch msb msb msb dummy cycles note: 1. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 60 figure 54. 2 x i/o fast read using 4 byte address sequence (2read4b) 21 345678 0 sclk si/sio0 so/sio1 cs# 9 10 21 22 23 24 bch 25 26 27 28 29 30 31 32 33 34 command configurable dummy cycle mode 3 mode 0 mode 3 mode 0 16 add cycles a31 a29 a27 a5 a3 a1 a4 a2 a a30 a28 a26 d6 d4 d7 d5 data out 1 data out 2 d2 d0 d3 d1 d0 d1 d6 d4 d7 d5 d2 d3 figure 55. 4 i/o fast read using 4 byte address sequence (4read4b) 21 345678 0 sclk sio0 sio1 sio2 sio3 cs# 9 1210 11 13 14 ech p4 p0 p5 p1 p6 p2 p7 p3 15 16 17 18 19 20 21 22 23 24 25 26 command configurable performance enhance indicator mode 3 mode 0 8 add cycles a21 a17 a13 a9 a5 a1 a8 a4 a a20 a16 a12 a23 a19 a15 a11 a7 a3 a10 a6 a2 a22 a18 a14 a28 a24 a29 a25 a30 a26 a31 a27 d4 d0 d5 d1 data out 1 data out 2 data out 3 d4 d0 d5 d1 d4 d0 d5 d1 d6 d2 d7 d3 d6 d2 d7 d3 d6 d2 d7 d3 mode 3 mode 0 dummy cycle note: 1. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. note: 1. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 61 figure 56. fast dt read (frdtrd4b) sequence (spi only) 23 31 32 33 34 35 8 7 0 0eh si/sio0 so/sio1 cs# a31 a30 a1 a0 sclk d7 d6 d5 d4 d3 d2 d1 d7d0 command 16 add cycles configurable dummy cycle data out 1 data out 2 mode 3 mode 0 figure 57. fast dual i/o dt read (2dtrd4b) sequence (spi only) 0 7 8 15 16 19 20 21 beh si/sio0 so/sio1 cs# a31 a30 a29 a28 a2 a0 a3 a1 sclk d6 d4 d2 d0 d6 d4 d2 d0 d6 d7 d5 d3 d1 d7 d5 d3 d1 d7 22 23 data out 1 data out 2 command 8 add cycles configurable dummy cycle mode 3 mode 0 note: 1. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. note: 1. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 62 figure 58. fast quad i/o dt read (4dtrd4b) sequence (spi mode) eeh sio0 sio1 cs# sio2 sio3 sclk p4 p0 d7 d3 d6 d2 d5 d1 d4 d0 d7 d3 d6 d2 d5 d1 d4 d0 d7 d6 d5 d4 performance enhance indicator 0 7 8 9 11 12 17 18 19 10 a0 a28 a24 a25a29 a26a30 a27a31 a4 a1a5 a2a6 a3 a7 command 4 add cycles p7 p6 p5 p1 p2 p3 configurable dummy cycle mode 3 mode 0 figure 59. fast quad i/o dt read (4dtrd4b) sequence (qpi mode) configurable dummy cycle eeh sio[3:0] cs# sclk p1 p0 h0 l0 h1 l1 h2 performance enhance indicator 0 mode 3 mode 0 1 2 3 5 6 11 12 13 4 command 4 add cycles a20 | a23 a24 | a27 a28 | a31 a16 | a19 a12 | a15 a8 | a11 a4 | a7 a0 | a3 note: 1. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. note: 1. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 63 figure 60. sector erase (se4b) sequence (spi mode) 21 3456789 0 31 30 393837 2 1 0 msb sclk cs# si 21h command mode 3 mode 0 32-bit address figure 61. block erase 32kb (be32k4b) sequence (spi mode) 21 3456789 0 msb sclk cs# si 5ch command mode 3 mode 0 31 30 393837 32-bit address 2 1 0 figure 62. block erase (be4b) sequence (spi mode) 21 3456789 0 msb sclk cs# si dch command mode 3 mode 0 31 30 393837 32-bit address 2 1 0 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 64 figure 63. page program (pp4b) sequence (spi mode) 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 31 30 29 0123 21 345678 9 10 0 76543 2 0 1 data byte 1 39 40 41 42 43 44 45 46 47 383736 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 2087 2086 2085 2084 2083 2082 2081 76543 2 0 1 2080 msb msb msb msb msb sclk cs# si sclk cs# si 12h command mode 3 mode 0 32-bit address a20 a21 a17 a16 a12 a8 a4 a0 a13 a9 a5 a1 4 4 4 0 0 0 5 5 5 1 1 1 21 3456789 8 address cycle data byte 2 data byte 3 data byte 4 0 a22 a18 a14 a10 a6 a2 a23 a24 a25 a26 a27 a28 a29 a30 a31 a19 a15 a11 a7 a3 6 6 6 2 2 2 7 7 7 3 3 3 sclk cs# sio0 sio1 sio3 sio2 3eh command 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 5 1 data byte 4 6 2 7 3 mode 3 mode 0 figure 64. 4 x i/o page program (4pp4b) sequence (spi mode only) mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 65 9-23. performance enhance mode the device could waive the command cycle bits if the two cycle bits after address cycle toggles. performance enhance mode is supported in both spi and qpi mode. in qpi mode, ebh "ech" "edh" "eeh" and spi ebh "ech" "edh" "eeh" commands support enhance mode. the performance enhance mode is not supported in dual i/o mode. to enter performance-enhancing mode, p[7:4] must be toggling with p[3:0]; likewise p[7:0]=a5h, 5ah, f0h or 0fh can make this mode continue and skip the next 4read instruction. to leave enhance mode, p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh, 00h, aah or 55h along with cs# is afterwards raised and then lowered. issuing ffh data cycle can also exit enhance mode. the system then will leave performance enhance mode and return to normal operation. after entering enhance mode, following cs# go high, the device will stay in the read mode and treat cs# go low of the frst clock as address instead of command cycle. another sequence of issuing 4read instruction especially useful in random access is : cs# goes low sending 4 read instruction 3-bytes or 4-bytes address interleave on sio3, sio2, sio1 & sio0 performance enhance toggling bit p[7:0] 4 dummy cycles (default) data out still cs# goes high cs# goes low (reduce 4 read instruction) 3-bytes or 4-bytes random access address. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 66 figure 65. 4 x i/o read enhance performance mode sequence (spi mode) 21 345678 0 sclk sio0 sio1 cs# 9 1210 11 13 14 ebh 15 16 n+1 ........... ...... ........... ........... n+7 n+9 n+13 17 18 19 20 21 22 n sio2 sio3 sio0 sio1 sio2 sio3 performance enhance indicator (note 1) sclk cs# performance enhance indicator (note 1) mode 3 mode 0 a21 a17 a13 a9 a5 a1 a8 a4 a a20 a16 a12 a23 a19 a15 a11 a7 a3 a10 a6 a2 a22 a18 a14 p4 p0 p5 p1 p6 p2 p7 p3 a21 a17 a13 a9 a5 a1 a8 a4 a a20 a16 a12 a23 a19 a15 a11 a7 a3 a10 a6 a2 a22 a18 a14 p4 p0 p5 p1 p6 p2 p7 p3 command configurable dummy cycle (note 2) 6 add cycles (note 2) 6 add cycles (note 2) d4 d0 d5 d1 data out 1 data out 2 data out n d4 d0 d5 d1 d4 d0 d5 d1 d6 d2 d7 d3 d6 d2 d7 d3 d6 d2 d7 d3 d4 d0 d5 d1 data out 1 data out 2 data out n d4 d0 d5 d1 d4 d0 d5 d1 d6 d2 d7 d3 d6 d2 d7 d3 d6 d2 d7 d3 mode 3 mode 0 configurable dummy cycle (note 2) notes: 1. if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator . 2. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. 3. please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 67 figure 66. 4 x i/o read enhance performance mode sequence (qpi mode) sclk sio[3:0] cs# data out data in ebh x p(7:4) p(3:0) x x x h0 l0 h1 l1 configurable dummy cycle (note 1) configurable dummy cycle (note 1) performance enhance indicator sclk sio[3:0] cs# data out msb lsb msb lsb msb lsb msb lsb x p(7:4) p(3:0) x x x h0 l0 h1 l1 performance enhance indicator n+1 ............. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 mode 3 mode 0 mode 0 6 address cycles (note) a20- a23 a16- a19 a12- a15 a8- a11 a4- a7 a0- a3 a20- a23 a16- a19 a12- a15 a8- a11 a4- a7 a0- a3 notes: 1. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. 2. please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 68 figure 67. 4 x i/o dt read enhance performance mode sequence (spi mode) edh sio0 sio1 cs# sio2 sio3 sclk p4 p0 d7 d3 d6 d2 d5 d1 d4 d0 d7 d3 d6 d2 d5 d1 d4 d0 d7 d3 d6 d2 d5 d1 d4 d0 performance enhance indicator 0 7 8 9 10 11 16 17 18 n a0 a20 a16 a17a21 a18a22 a19a23 a4 a1a5 a2a6 a3 a7 command 3 add cycles p7 p6 p5 p1 p2 p3 configurable dummy cycle mode 3 mode 0 sio0 sio1 cs# sio2 sio3 sclk p4 p0 d7 d3 d6 d2 d5 d1 d4 d0 d7 d3 d6 d2 d5 d1 d4 d0 performance enhance indicator a0 a20 a16 a17a21 a18a22 a19a23 a4 a1a5 a2a6 a3 a7 3 add cycles p7 p6 p5 p1 p2 p3 configurable dummy cycle n+1 n+4 mode 3 mode 0 notes: 1. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. 2. please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 69 figure 68. 4 x i/o dt read enhance performance mode sequence (qpi mode) configurable dummy cycle edh sio[3:0] cs# sclk p1 p0 h0 l0 h1 l1 hn ln performance enhance indicator 0 mode 3 mode 0 1 2 3 4 5 10 11 12 n command 3 add cycles a20 | a23 a16 | a19 a12 | a15 a8 | a11 a4 | a7 a0 | a3 configurable dummy cycle sio[3:0] cs# sclk p1 p0 h0 l0 h1 l1 performance enhance indicator n+1 n+4 3 add cycles a20 | a23 a16 | a19 a12 | a15 a8 | a11 a4 | a7 a0 | a3 mode 3 mode 0 notes: 1. confguration dummy cycle numbers will be different depending on the bit6 & bit7 (dc0 & dc1) setting in confguration register. 2. please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 70 9-24. performance enhance mode reset to conduct the performance enhance mode reset operation in spi mode, ffh data cycle(8 clocks in 3-byte address mode)/3ffh data cycle(10 clocks in 4-byte address mode), should be issued in 1i/o sequence. in qpi mode, ffffffffh data cycle(8 clocks in 3-byte address mode)/ffffffffffh data cycle (10 clocks in 4-byte address mode), in 4i/o should be issued. if the system controller is being reset during operation, the fash device will return to the standard spi operation. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. figure 69. performance enhance mode reset for fast read quad i/o (spi mode) 21 34567 mode 3 don?t care mode mode 3 mode sclk sio0 cs# sio1 ffh sio2 sio3 mode bit reset for quad i/o don?t care don?t care figure 70. performance enhance mode reset for fast read quad i/o (qpi mode) 21 34567 mode 3 mode mode 3 mode sclk sio[3:0] cs# ffffffffh mode bit reset for quad i/o mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 71 figure 71. performance enhance mode reset for fast read quad i/o using 4byte address sequence (spi mode) mode 3 0 1 2 3 4 5 6 7 8 9 mode mode 3 mode sclk sio0 cs# sio1 sio2 sio3 mode bit reset for quad i/o don?t care 3ffh don?t care don?t care figure 72. performance enhance mode reset for fast read quad i/o using 4byte address sequence (qpi mode) mode 3 0 1 2 3 4 5 6 7 8 9 mode mode 3 mode sclk cs# mode bit reset for quad i/o ffffffffffh sio[3:0] mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 72 the wrap around unit is defned within the 256byte page, with random initial address. it is defned as wrap-around mode disable for the default state of the device. to exit wrap around, it is required to issue another c0 command in which data=1xh. otherwise, wrap around status will be retained until power down or reset command. to change wrap around depth, it is requried to issue another c0 command in which data=0xh. qpi ebh "ech" and spi ebh "ech" support wrap around feature after wrap around is enabled. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. data wrap around wrap depth 00h yes 8-byte 01h yes 16-byte 02h yes 32-byte 03h yes 64-byte 1xh no x 0 cs# sclk sio c0h d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 6 7 8 9 10 1 12 13 14 15 5 mode 3 mode 0 figure 73. spi mode figure 74. qpi mode 0 cs# sclk sio[3:0] h0 msb lsb l0 c0h 1 2 3 mode 3 mode 0 note: msb=most signifcant bit lsb=least signifcant bit 9-25. burst read to set the burst length, following command operation is required to issue command: c0h in the frst byte (8-clocks), following 4 clocks defning wrap around enable with 0h and disable with1h. the next 4 clocks are to defne wrap around depth. their defnitions are as the following table: mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 73 fast boot register (fbr) 9-26. fast boot the fast boot feature provides the ability to automatically execute read operation after power on cycle or reset without any read instruction. a fast boot register is provided on this device. it can enable the fast boot function and also defne the number of delay cycles and start address (where boot code being transferred). instruction wrfbr (write fast boot register) and esfbr (erase fast boot register) can be used for the status confguration or alternation of the fast boot register bit. rdfbr (read fast boot register) can be used to verify the program state of the fast boot register. the default number of delay cycles is 13 cycles, and there is a 16bytes boundary address for the start of boot code access. when cs# starts to go low, data begins to output from default address after the delay cycles (default as 13 cycles). after cs# returns to go high, the device will go back to standard spi mode and user can start to input command. in the fast boot data out process from cs# goes low to cs# goes high, a minimum of one byte must be output. once fast boot feature has been enabled, the device will automatically start a read operation after power on cycle, reset command, or hardware reset operation. the fast boot feature can support single i/o and quad i/o interface. if the qe bit of status register is 0, the data is output by single i/o interface. if the qe bit of status register is set to 1, the data is output by quad i/o interface. bits description bit status default state type 31 to 4 fbsa (fastboot start address) 16 bytes boundary address for the start of boot code access. fffffff non- volatile 3 x 1 non- volatile 2 to 1 fbsd (fastboot start delay cycle) 00: 7 delay cycles 01: 9 delay cycles 10: 11 delay cycles 11: 13 delay cycles 11 non- volatile 0 fbe (fastboot enable) 0=fastboot is enabled. 1=fastboot is not enabled. 1 non- volatile note: if fbsd = 11, the maximum clock frequency is 133 mhz if fbsd = 10, the maximum clock frequency is 104 mhz if fbsd = 01, the maximum clock frequency is 84 mhz if fbsd = 00, the maximum clock frequency is 70 mhz mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 74 figure 75. fast boot sequence (qe=0) n+2 delay cycles 0 7 6543210 data out 1 high impedance msb 7 6543210 data out 2 msb 7 sclk si cs# so mode 3 mode 0 - - - - - - n n+1 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n+15 don?t care or high impedance msb figure 76. fast boot sequence (qe=1) 4 0 5 1 5 1 4 4 4 0 0 0 5 1 -------n high impedance 0 6 2 6 2 6 2 7 3 7 3 7 3 6 2 7 3 sclk cs# sio0 sio1 sio3 sio2 msb delay cycles n+1 n+2 n+3 n+5 n+6 n+7 n+8 n+9 mode 3 mode 0 data out 1 5 1 high impedance high impedance high impedance data out 2 data out 3 data out 4 4 5 6 7 note: if fbsd = 11, delay cycles is 13 and n is 12. if fbsd = 10, delay cycles is 1 1 and n is 10. if fbsd = 01, delay cycles is 9 and n is 8. if fbsd = 00, delay cycles is 7 and n is 6. note: if fbsd = 11, delay cycles is 13 and n is 12. if fbsd = 10, delay cycles is 1 1 and n is 10. if fbsd = 01, delay cycles is 9 and n is 8. if fbsd = 00, delay cycles is 7 and n is 6. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 75 figure 77. read fast boot register (rdfbr) sequence 21 3456789 0 sclk cs# si so 16h command mode 3 37 10 38 39 40 41 mode 0 msb 7 6 7 6 5 25 2426 high-z msb data out 1 data out 2 figure 78. write fast boot register (wrfbr) sequence 21 3456789 0 msb sclk cs# si 17h command mode 3 37 38 39 mode 0 fast boot register so high-z 7 6 25 2426 10 5 figure 79. erase fast boot register (esfbr) sequence 21 34567 high-z 0 18h command sclk si cs# so mode 3 mode 0 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 76 figure 80. sector erase (se) sequence (spi mode) 21 3456789 29 30 31 0 a23 a22 a2 a1 a0 msb sclk cs# si 20h command mode 3 mode 0 24-bit address (note) note: please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. figure 81. sector erase (se) sequence (qpi mode) sclk sio[3:0] cs# 20h 2 3 5 7 10 msb 4 6 command mode 3 mode 0 24-bit address (note) a20- a23 a16- a19 a12- a15 a8- a11 a4- a7 a0- a3 note: please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. 9-27. sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see "table 4. memory organization" ) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to defne ear bit. address bits [am-a12] (am is the most signifcant address) select the sector address. to enter the 4-byte address mode, please refer to the enter 4-byte mode (en4b) mode section. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte or 4-byte address on si cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the sector erase cycle is in progress. the wip sets 1 during the tse timing, and clears when sector erase cycle is completed, and the write enable latch (wel) bit is cleared. if the block is protected by bp bits (wpsel=0; block protect mode) or spb/dpb (wpsel=1; advanced sector protect mode), the sector erase (se) instruction will not be executed on the block. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 77 9-28. block erase (be32k) the block erase (be32k) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 32k-byte block erase operation. a write enable (wren) instruction be executed to set the write enable latch (wel) bit before sending the block erase (be32k). any address of the block (see "table 4. memory organization" ) is a valid address for block erase (be32k) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a15] (am is the most signifcant address) select the 32kb block address. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to defne ear bit. to enter the 4-byte address mode, please refer to the enter 4-byte mode (en4b) mode section. the sequence of issuing be32k instruction is: cs# goes low sending be32k instruction code 3-byte or 4-byte address on sics# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the self-timed block erase cycle time (tbe32k) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while during the block erase cycle is in progress. the wip sets during the tbe32k timing, and clears when block erase cycle is completed, and the write enable latch (wel) bit is cleared. if the block is protected by bp bits (wpsel=0; block protect mode) or spb/dpb (wpsel=1; advanced sector protect mode), the block erase (be32k) instruction will not be executed on the block. figure 82. block erase 32kb (be32k) sequence (spi mode) 21 3456789 29 30 31 0 msb sclk cs# si 52h command mode 3 mode 0 24-bit address (note) a23 a22 a2 a1 a0 note: please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. figure 83. block erase 32kb (be32k) sequence (qpi mode) sclk sio[3:0] cs# 52h 2 3 5 7 10 msb 4 6 command mode 3 mode 0 24-bit address (note) a20- a23 a16- a19 a12- a15 a8- a11 a4- a7 a0- a3 note: please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 78 9-29. block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the block erase (be). any address of the block ( please refer to "table 4. memory organization" ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to defne ear bit. to enter the 4-byte address mode, please refer to the enter 4-byte mode (en4b) mode section. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte or 4-byte address on si cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the block erase cycle is in progress. the wip sets during the tbe timing, and clears when block erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp bits (wpsel=0; block protect mode) or spb/dpb (wpsel=1; advanced sector protect mode), the block erase (be) instruction will not be executed on the block. figure 84. block erase (be) sequence (spi mode) 21 3456789 29 30 31 0 msb sclk cs# si d8h command mode 3 mode 0 24-bit address (note) a23 a22 a2 a1 a0 figure 85. block erase (be) sequence (qpi mode) sclk sio[3:0] cs# d8h 2 3 10 msb 4 5 6 7 command mode 3 mode 0 24-bit address (note) a20- a23 a16- a19 a12- a15 a8- a11 a4- a7 a0- a3 note: please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. note: please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 79 9-30. chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes lowsending ce instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the chip erase cycle is in progress. the wip sets during the tce timing, and clears when chip erase cycle is completed, and the write enable latch (wel) bit is cleared. when the chip is under "block protect (bp) mode" (wpsel=0). the chip erase (ce) instruction will not be executed, if one (or more) sector is protected by bp3-bp0 bits. it will be only executed when bp3-bp0 all set to "0". when the chip is under "advances sector protect mode" (wpsel=1). the chip erase (ce) instruction will be executed on unprotected block. the protected block will be skipped. if one (or more) 4k byte sector was protected in top or bottom 64k byte block, the protected block will also skip the chip erase command. figure 86. chip erase (ce) sequence (spi mode) 21 34567 0 60h or c7h sclk si cs# command mode 3 mode 0 figure 87. chip erase (ce) sequence (qpi mode) sclk sio[3:0] cs# 60h or c7h 0 1 command mode 3 mode 0 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 80 9-31. page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. if the entire 256 data bytes are going to be programmed, a7-a0 (the eight least signifcant address bits) should be set to 0. the last address byte (the 8 least signifcant address bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to defne ear bit. to enter the 4-byte address mode, please refer to the enter 4-byte mode (en4b) mode section. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte or 4-byte address on si at least 1-byte on data on si cs# goes high. the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the page program cycle is in progress. the wip sets during the tpp timing, and clears when page program cycle is completed, and the write enable latch (wel) bit is cleared. if the page is protected by bp bits (wpsel=0; block protect mode) or spb/dpb (wpsel=1; advanced sector protect mode), the page program (pp) instruction will not be executed. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 81 figure 88. page program (pp) sequence (spi mode) 4241 43 44 45 46 47 48 49 50 52 53 54 55 40 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 0 76543 2 0 1 data byte 1 39 51 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 76543 2 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02h command mode 3 mode 0 24-bit address (note) note: please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. figure 89. page program (pp) sequence (qpi mode) sclk sio[3:0] cs# data byte 2 data in 02h h0 l0 h1 l1 h2 l2 h3 l3 h255 l255 data byte 1 data byte 3 data byte 4 data byte 256 command mode 3 mode 0 24-bit address (note) a20- a23 0 1 2 3 4 5 6 7 8 9 a16- a19 a12- a15 a8- a11 a4- a7 a0- a3 note: please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 82 9-32. 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must be executed to set the write enable latch (wel) bit and quad enable (qe) bit must be set to "1" before sending the quad page program (4pp). the quad page programming takes four pins: sio0, sio1, sio2, and sio3 as address and data input, which can improve programmer performance and the effectiveness of application. the other function descriptions are as same as standard page program. the default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or to defne ear bit. to enter the 4-byte address mode, please refer to the enter 4-byte mode (en4b) mode section. the sequence of issuing 4pp instruction is: cs# goes low sending 4pp instruction code 3-byte or 4-byte address on sio[3:0] at least 1-byte on data on sio[3:0]cs# goes high. if the page is protected by bp bits (wpsel=0; block protect mode) or spb/dpb (wpsel=1; advanced sector protect mode), the quad page program (4pp) instruction will not be executed. a20 a21 a17 a16 a12 a8 a4 a0 a13 a9 a5 a1 4 4 4 4 0 0 0 0 5 5 5 5 1 1 1 1 21 3456789 6 address cycle data byte 1 data byte 2 data byte 3 data byte 4 0 a22 a18 a14 a10 a6 a2 a23 a19 a15 a11 a7 a3 6 6 6 6 2 2 2 2 7 7 7 7 3 3 3 3 sclk cs# sio0 sio1 sio3 sio2 38h command 10 11 12 13 14 15 16 17 18 19 20 21 mode 3 mode 0 figure 90. 4 x i/o page program (4pp) sequence (spi mode only) note: please note the address cycles above are based on 3-byte address mode. for 4-byte address mode, the address cycles will be increased. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 83 9-33. deep power-down (dp) the deep power-down (dp) instruction is for setting the device to minimum power consumption (the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/program/erase instruction are ignored. when cs# goes high, it's only in deep power-down mode not standby mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes lowsending dp instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction and softreset command. (those instructions allow the id being reading out). when power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for dp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode. figure 91. deep power-down (dp) sequence (spi mode) 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9h command mode 3 mode 0 figure 92. deep power-down (dp) sequence (qpi mode) sclk sio[3:0] cs# b9h 0 1 t dp deep power-down mode stand-by mode command mode 3 mode 0 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 84 9-34. enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. while device is in 4k-bit secured otpmode, main array access is not available. the additional 4k-bit secured otp is independent from main array and may be used to store unique serial number for system identifer. after entering the secured otp mode, follow standard read or program procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. please note that after issuing enso command user can only access secure otp region with standard read or program procedure. furthermore, once security otp is lock down, only read related commands are valid. 9-35. exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 9-36. read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes lowsending rdscur instructionsecurity register data out on so cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 9-37. write security register (wrscur) the wrscur instruction is for changing the values of security register bits. the wren (write enable) instruction is required before issuing wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 4k-bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 85 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wpsel e_fail p_fail reserved esb (erase suspend bit) psb (program suspend bit) ldso (indicate if lock-down) secured otp indicator bit 0=normal wp mode 1=individual mode (default=0) 0=normal erase succeed 1=indicate erase failed (default=0) 0=normal program succeed 1=indicate program failed (default=0) - 0=erase is not suspended 1= erase suspended (default=0) 0=program is not suspended 1= program suspended (default=0) 0 = not lock- down 1 = lock-down (cannot program/ erase otp) 0 = non- factory lock 1 = factory lock non-volatile bit (otp) volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit (otp) non-volatile bit (otp) table 8. security register defnition security register the defnition of the security register bits is as below: write protection selection bit. please reference to " write protection selection bit" erase fail bit. the erase fail bit is a status fag, which shows the status of last erase operation. it will be set to "1", if the erase operation fails or the erase region is protected. it will be set to "0", if the last operation is success. please note that it will not interrupt or stop any operation in the fash memory . program fail bit. the program fail bit is a status fag, which shows the status of last program operation. it will be set to "1", if the program operation fails or the program region is protected. it will be set to "0", if the last operation is success. please note that it will not interrupt or stop any operation in the fash memory . erase suspend bit. erase suspend bit (esb) indicates the status of erase suspend operation. users may use esb to identify the state of fash memory. after the fash memory is suspended by erase suspend command, esb is set to "1". esb is cleared to "0" after erase operation resumes. program suspend bit. program suspend bit (psb) indicates the status of program suspend operation. users may use psb to identify the state of fash memory. after the fash memory is suspended by program suspend command, psb is set to "1". psb is cleared to "0" after program operation resumes. secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory or not. when it is "0", it indicates non-factory lock; "1" indicates factory-lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for customer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be updated any more. while it is in 4k-bit secured otp mode, main array access is not allowed. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 86 9-38. write protection selection (wpsel) there are two write protection methods provided on this device, (1) block lock (bp) protection mode (2) advanced sector protection mode. if wpsel=0, fash is under bp protection mode. if wpsel=1, fash is under advanced sector protection mode. the default value of wpsel is 0. wpsel command can be used to set wpsel=1. please note that wpsel is an otp bit. once wpsel is set to 1, there is no chance to recovery wpsel back to 0. if the fash is put on bp mode, the advanced sector protection mode is disabled. contrarily, if fash is on the advanced sector protection mode, the bp mode is disabled. every time after the system is powered-on, and the security register bit 7 is checked to be wpsel=1, all the blocks or sectors will be write protected by dynamic protected bit (dpb) in default. user may only unlock the blocks or sectors via gbulk instruction. program or erase functions can only be operated after the unlock instruction is conducted. when wpsel = 0: block lock (bp) protection mode, array is protected by bp3~bp0 and bp bits are protected by srwd=1 and wp#=0, where srwd is bit 7 of status register that can be set by wrsr command. when wpsel =1: advanced sector protection mode, blocks are individually protected by their own spb or dpb lock bits which are set to 1 after power up. when the system accepts and executes wpsel instruction, the bit 7 in security register will be set. it will activate wrlr, rdlr, wrpass, rdpass, passulk, wrspb, esspb, spblk, rdspblk, wrdpb, rddpb, gblk, gbulk etc instructions to conduct block lock protection and replace the original software protect mode (spm) use (bp3~bp0) indicated block methods. under the advanced sector protection mode (wpsel=1), hardware protection is performed by driving wp#=0. once wp#=0 all array blocks/sectors are protected regardless of the contents of spb or dpb lock bits. the sequence of issuing wpsel instruction is: cs# goes low sending wpsel instruction to enter the individual block protect mode cs# goes high. write protection selection start (default in bp mode) set wpsel bit wpsel=0 wpsel=1 bit 2 =0 bit 1 =0 block protection (bp) advance sector protection set lock register password protection solid protection dynamic protection mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 87 figure 93. wpsel flow rdscur command rdsr command rdscur command wpsel set successfully yes yes wpsel set fail no start wpsel=1? wip=0? no wpsel disable, block protected by bp[3:0] yes no wren command wpsel=1? wpsel command wpsel enable. block protected by advance sector protection mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 88 9-39. advanced sector protection there are two ways to implement software advanced sector protection on this device: password method or sol id method. through these two protection methods, user can disable or enable the programming or erasing op eration to any individual sector or all sectors. there is a non-volatile (spb) and volatile (dpb) protection bit related to the single sector in main fash array. each of the sectors is protected from programming or erasing operation when the bit is set. the temporary unprotect solid write protect bit (uspb) can temporarily unprotect the sectors protected by spb. the fgure below helps describing an overview of these methods. the device is default to the solid mode when shipped from factory. the detail algorithm of advanced sector protection is shown as follows: figure 94. advanced sector protection overview start bit 1=0 bit 2=0 password protection mode set lock register ? set spb lock bit ? spblk = 0 spblk = 1 spb lock bit unlocked spb is changeable spb access register (spb) dynamic protect bit register (dpb) spb=1 write protect spb=0 write unprotect spb 0 spb 1 spb 2 : : spb n-1 spb n sa 0 sa 1 sa 2 : : sa n-1 sa n dpb 0 dpb 1 dpb 2 : : dpb n-1 dpb n spb lock bit locked all spb can not be changeable solid protection mode set 64 bit password sector array dpb=1 sector protect dpb=0 sector unprotect temporary unprotect spb bit (uspb) uspb=0 spb bit is disabled uspb=1 spb bit is effective uspb mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 89 9-39-1. lock register user can choose favorite sector protecting method via setting lock register bits 1 and 2. lock register is a 16- bit one-time programmable register. once bit 1 or bit 2 has been programmed (cleared to "0"), they will be locked in that mode and the others will be disabled permanently. bit 1 and bit 2 can not be programmed at the same time, otherwise the device will abort the operation. if user selects password protection mode, the password setting is required. user can set password by issuing wrpass command. lock register bit 15-3 bit 2 bit 1 bit0 reserved password protection mode lock bit solid protection mode lock bit reserved x 0=password protection mode enable 1= password protection mode not enable (default =1) 0=solid protection mode enable 1= solid protection mode not enable (default =1) x otp otp otp otp figure 95. read lock register (rdlr) sequence 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 high-z msb 15 14 13 12 11 10 9 8 register out register out msb 7 sclk si cs# so 2dh mode 3 mode 0 figure 96. write lock register (wrlr) sequence (spi mode) 21 345678 9 10 11 12 13 14 15 lock register in 0 msb sclk si cs# so 2ch high-z command mode 3 mode 0 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 notes: 1. while bit 2 or bit 1 has been "0" status, other bits can't be changed any more. if set lock register program mode, program fail will be set to "1". mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 90 9-39-2. spb lock bit (spblb) the solid protection bit lock bit (spblb) is assigned to control all spb status. it is unique and volatile. the default status of this register is determined by lock register bit 1 and bit 2 status. refer to spb lock register for more spb lock information. when under solid protect mode, there is no software command sequence requested to unlock this bit. to clear the spb lock bit, just take the device through a reset or a power-up cycle. when under password protection mode, in order to prevent modifcation, the spb lock bit must be set after all spbs are setting the desired status. spb lock register bit description bit status default type 7-1 reserved x 0000000 volatile 0 spblk (lock spb bit) 0= spb bit protected 1= spb bit unprotected solid protected mode=1 password protected mode=0 volatile figure 97. spb lock bit set (spblk) sequence 21 34567 high-z 0 a6h command sclk si cs# so mode 3 mode 0 figure 98. read spb lock register (rdspblk) sequence 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 high-z msb 7 6543210 register out register out msb 7 sclk si cs# so a7h mode 3 mode 0 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 91 9-39-3. solid protection bits the solid write protection bit (spb) is a nonvolatile bit with the same endurances as the flash memory. it is assigned to each sector individually. when a spb is set to 1, the associated sector may be protected, preventing any program or erase operation on this sector. the spb bits are set individually by wrspb command. however, it cannot be cleared individually. issuing the esspb command will erase all spb in the same time. to unprotect a protected sector (corresponding spb cleared to 0), the spb lock bit must be unlocked frst. under password protection mode (lock register bit 2 set as "0"), a passulk command is requested before unlocking spb lock bit. however, while the device is under solid protection mode (lock register bit 1 set as "0"), just a reset or a power-up cycle can unlock the spb lock bit. after the spb lock bit unlocked, the spb status can be changed for desired settings. to lock the solid protection bits after the modifcation has fnished, the spb lock bit must be set once again. to verify the programming state of the spb for a given sector, issuing a rdspb command to the device is required. note: 1. once spb lock bit is set, its program or erase command will not be executed and time-out without programming or erasing the spb. spb register bit description bit status default type 7 to 0 spb (solid protected bit) 00h= spb for the sector address unprotected ffh= spb for the sector address protected 00h non-volatile mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 92 figure 99. read spb status (rdspb) sequence 21 3456789 0 msb sclk cs# si so e2h command mode 3 37 38 39 40 41 42 mode 0 32-bit address a31 a30 a2 a1 a0 7 6543210 high-z msb data out 43 44 45 46 47 figure 100. spb erase (esspb) sequence 21 34567 high-z 0 e4h command sclk si cs# so mode 3 mode 0 figure 101. spb program (wrspb) sequence 21 3456789 0 msb sclk cs# si e3h command mode 3 37 38 39 mode 0 32-bit address a31 a30 a2 a1 a0 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 93 9-39-4. dynamic write protection bits the dynamic protection features a volatile type protection to each individual sector. it can protect sectors from unintentional change, and is easy to disable when there are necessary changes. all dpbs are default as protected (ffh) after reset or upon pow er up cycle. via setting up dynamic protection bit (dpb) by write dpb command (wrdpb), user can cancel the dynamic protection of associated sector. the dynamic protection only works on those unprotected sectors whose spbs are cleared. after the dpb state is cleared to 0, the sector can be modifed if the spb state is unprotected state. dpb register bit description bit status default type 7 to 0 dpb (dynamic protected bit) 00h= dpb for the sector address unprotected ffh= dpb for the sector address protected ffh volatile figure 102. read dpb register (rddpb) sequence 21 3456789 0 msb sclk cs# si so e0h command mode 3 37 38 39 40 41 42 mode 0 32-bit address a31 a30 a2 a1 a0 7 6543210 high-z msb data out 43 44 45 46 47 figure 103. write dpb register (wrdpb) sequence 21 3456789 0 msb sclk cs# si e1h command mode 3 37 38 39 40 41 42 mode 0 32-bit address a31 a30 a2 a1 a0 7 6543210 msb data byte 1 43 44 45 46 47 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 94 9-39-5. temporary un-protect solid write protect bit (uspb) temporary un-protect solid write protect bit is volatile bit. software can temporarily unprotect write protect sectors despite of spbs' property when dpbs are cleared. while the uspb=1, all the spbs property is masked. notes: 1. upon power up, the uspb status is default protected. the uspb can be unprotected (to 0) or protected (to 1) as often as needed. the hardware reset will reset uspb/dpb to their default values. 2. please refer to "9-39-7. sector protection states summary table" for the sector state with the protection status of dpb/spb/uspb bits. 9-39-6. gang block lock/unlock (gblk/gbulk) these instructions are only effective after wpsel was executed. the gblk/gbulk instruction is a chip-based protected or unprotected operation. it can enable or disable all dpb. the wren (write enable) instruction is required before issuing gblk/gbulk instruction. the sequence of issuing gblk/gbulk instruction is: cs# goes low send gblk/gbulk (7eh/98h) instruction cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the cs# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. 9-39-7. sector protection states summary table protection status sector state dpb bit spb bit uspb bit 0 0 0 unprotect 0 0 1 unprotect 0 1 0 unprotect 0 1 1 protect 1 0 0 protect 1 0 1 protect 1 1 0 protect 1 1 1 protect mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 95 9-39-8. password protection mode the security level of password protection method is higher than the solid protection mode. the 64 bit password is requested before modify spb lock bit status. when device is under password protection mode, the spb lock bit is set 0, after a power-up cycle or reset command. a correct password is required for passulk command, to unlock the spb lock bit. await 2us is necessary to unlocked the device after valid password is given. after that, the spb bits are allows to be changed. the passulk command are issued slower than 2 s every time, to prevent hacker from trying all the 64-bit password combinations. to place the device in password protection mode, a few more steps are required. first, prior to entering the password protection mode, it is necessary to set a 64-bit password to verify it. password verifcation is only allowed during the password programming operation. second, the password protection mode is then activated by programming the password protection mode lock bit to0. this operation is not reversible. once the bit is programmed, it cannot be erased, and the device remains permanently in password protection mode, and the 64-bit password can neither be retrieved nor reprogrammed. moreover, all commands to the address where the password is stored are disabled. the password is all 1s when shipped from the factory, it is only capable of programming "0"s under wrpass command. all 64-bit password combinations are valid as a password. no special address is required for programming the password. the password is no longer readable after the password protection mode is selected by programming lock register bit 2 to "0". once sector under protected status, device will ignores the program/erase command, enable status polling and returns to read mode without contents change. the dpb, spb and spb lock bit status of each sector can be verifed by issuing rdspb, rddpb, rdspblk commands. the unlock operation may fail if the password provided by passulk command does not match the previously entered password. it causes the same result when a programming operation is performed on a protected sector. the p_err bit is set to 1 and the wip bit remains set. it is not allowed to execute the passulk command faster than every 100us 20us. the reason behind it is to make it impossible to hack into the system by running through all the combinations of a set of 64-bit password (58 million years). to verify if the device has completed the passulk command and is available to process a new password command, the read status register command is needed to read the wip bit. when a valid password is provided the passulk command does not insert the 100us delay before returning the wip bit to zero. it is not feasible to set the spb lock bit if the password is missing after the password mode is selected. password register (pass) bits field name function type default state description 63 to 0 pwd hidden password otp ffffffffffffffffh non-volatile otp storage of 64 bit password. the password is no longer readable after the password protection mode is selected by programming lock register bit 2 to zero. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 96 figure 104. read password register (rdpass) sequence 21 3456789 0 sclk cs# si so 27h command mode 3 69 70 71 72 73 mode 0 msb 7 6 7 6 57 5658 high-z msb data out 1 data out 2 figure 105. write password register (wrpass) sequence 21 3456789 0 msb sclk cs# si 28h command mode 3 69 70 71 mode 0 password 7 6 58 57 56 so high-z figure 106. password unlock (passulk) sequence 21 3456789 0 msb sclk cs# si so 29h high-z command mode 3 69 70 71 mode 0 password 7 6 58 57 56 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 97 9-40. program/erase suspend/resume the device allow the interruption of sector-erase, block-erase or page-program operations and conduct other operations. after issue suspend command, the system can determine if the device has entered the erase-suspended mode through bit2 (psb) and bit3 (esb) of security register. (please refer to "table 8. security register defnition" ) the latency time of erase operation : suspend to suspend ready timing: 25us. resume to another suspend timing: 1ms. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 9-41. erase suspend erase suspend allow the interruption of all erase operations. after the device has entered erase-suspended mode, the system can read any sector(s) or block(s) except those being erased by the suspended erase operation. reading the sector or block being erase suspended is invalid. after erase suspend, wel bit will be clear, only read related, resume and reset command can be accepted. (including: 03h, 0bh, 3bh, 6bh, bbh, ebh, ech, edh, eeh, 0ch, bch, 3ch, 5ah, c0h, 06h, 04h, 2bh, 9fh, afh, 05h, abh, 90h, b1h, c1h, b0h, 30h, 66h, 99h, 00h, 35h, f5h, 15h, 2dh, 27h, a7h, e2h, e0h, 16h) if the system issues an erase suspend command after the sector erase operation has already begun, the device will not enter erase-suspended mode until 20us time has elapsed. erase suspend bit (esb) indicates the status of erase suspend operation. users may use esb to identify the state of fash memory. after the fash memory is suspended by erase suspend command, esb is set to "1". esb is cleared to "0" after erase operation resumes. 9-42. program suspend program suspend allows the interruption of all program operations. after the device has entered program- suspended mode, the system can read any sector(s) or block(s) except those be ing programmed by the suspended program operation. reading the sector or block being program suspended is invalid. after program suspend, wel bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0bh, 3bh, 6bh, bbh, ebh, ech, edh, eeh, 0ch, bch, 3ch, 5ah, c0h, 06h, 04h, 2bh, 9fh, afh, 05h, abh, 90h, b1h, c1h, b0h, 30h, 66h, 99h, 00h, 35h, f5h, 15h, 2dh, 27h, a7h, e2h, e0h, 16h) program suspend bit (psb) indicates the status of program suspend operation. users may use psb to identify the state of fash memory. after the fash memory is suspended by program suspend command, psb is set to "1". psb is cleared to "0" after program operation resumes. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 98 figure 107. suspend to read latency cs# program latency erase latency suspend command [b0] read command figure 108. resume to read latency cs# tse/tbe/tpp resume command [30] read command figure 109. resume to suspend latency cs# 1ms resume command [30] suspend command [b0] mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 99 9-43. write-resume the write operation is being resumed when write-resume instruction issued. esb or psb (suspend status bit) in status register will be changed back to 0. the operation of write-resume is as follows: cs# drives low send write resume command cycle (30h) drive cs# high. by polling busy bit in status register, the internal write operation status could be checked to be completed or not. the user may also wait the time lag of tse, tbe, tpp for sector-erase, block-erase or page-programming. wren (command "06") is not required to issue before resume. resume to another suspend operation requires latency time of 1ms. please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resumed. to restart the write command, disable the "performance enhance mode" is required. after the "performance enhance mode" is disabled, the write-resume command is effective. 9-44. no operation (nop) the no operation command is only able to terminate the reset enable (rsten) command and will not affect any other command. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care during spi mode. 9-45. software reset (reset-enable (rsten) and reset (rst)) the software reset operation combines two instructions: reset-enable (rsten) command and reset (rst) command. it returns the device to standby mode. all the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. to execute reset command (rst), the reset-enable (rsten) command must be executed frst to perform the reset operation. if there is any other command to interrupt after the reset-enable command, the reset-enable will be invalid. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. if the reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. the reset time is different depending on the last operation. for details, please refer to "table 13. reset timing- (other operation)" for tready2. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 100 figure 110. software reset recovery cs# mode 66 99 tready2 stand-by mode figure 111. reset sequence (spi mode) cs# sclk sio0 66h mode 3 mode 0 mode 3 mode 0 99h command command tshsl figure 112. reset sequence (qpi mode) mode 3 sclk sio[3:0] cs# mode 3 99h 66h mode 0 mode 3 mode 0 mode 0 command command tshsl note: refer to "table 13. reset timing-(other operation)" for tready2. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 101 9-46. read sfdp mode (rdsfdp) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial fash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. the sequence of issuing rdsfdp instruction is cs# goes lowsend rdsfdp instruction (5ah)send 3 address bytes on si pinsend 1 dummy byte on si pinread sfdp code on soto end rdsfdp operation can use cs# to high at any time during data out. sfdp is a jedec standard, jesd216. figure 113. read serial flash discoverable parameter (rdsfdp) sequence 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 5ah command mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 102 table 9. signature and parameter identifcation data values description comment add (h) (byte) dw add (bit) data (h/b) note1 data (h) sfdp signature fixed: 50444653h 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h sfdp minor revision number start from 00h 04h 07:00 00h 00h sfdp major revision number start from 01h 05h 15:08 01h 01h number of parameter headers this number is 0-based. therefore, 0 indicates 1 parameter header. 06h 23:16 01h 01h unused 07h 31:24 ffh ffh id number (jedec) 00h: it indicates a jedec specifed header. 08h 07:00 00h 00h parameter table minor revision number start from 00h 09h 15:08 00h 00h parameter table major revision number start from 01h 0ah 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 0bh 31:24 09h 09h parameter table pointer (ptp) first address of jedec flash parameter table 0ch 07:00 30h 30h 0dh 15:08 00h 00h 0eh 23:16 00h 00h unused 0fh 31:24 ffh ffh id number (macronix manufacturer id) it indicates macronix manufacturer id 10h 07:00 c2h c2h parameter table minor revision number start from 00h 11h 15:08 00h 00h parameter table major revision number start from 01h 12h 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 13h 31:24 04h 04h parameter table pointer (ptp) first address of macronix flash parameter table 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h unused 17h 31:24 ffh ffh mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 103 table 10. parameter table (0): jedec flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) note1 data (h) block/sector erase sizes 00: reserved, 01: 4kb erase, 10: reserved, 11: not support 4kb erase 30h 01:00 01b e5h write granularity 0: 1byte, 1: 64byte or larger 02 1b write enable instruction required for writing to volatile status registers 0: not required 1: required 00h to be written to the status register 03 0b write enable opcode select for writing to volatile status registers 0: use 50h opcode, 1: use 06h opcode note: if target fash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b unused contains 111b and can never be changed 07:05 111b 4kb erase opcode 31h 15:08 20h 20h (1-1-2) fast read (note2) 0=not support 1=support 32h 16 1b f3h address bytes number used in addressing fash array 00: 3byte only, 01: 3 or 4byte, 10: 4byte only, 11: reserved 18:17 01b double transfer rate (dtr) clocking 0=not support 1=support 19 0b (1-2-2) fast read 0=not support 1=support 20 1b (1-4-4) fast read 0=not support 1=support 21 1b (1-1-4) fast read 0=not support 1=support 22 1b unused 23 1b unused 33h 31:24 ffh ffh flash memory density 37h:34h 31:00 1fff ffffh (1-4-4) fast read number of wait states (note3) 0 0000b: wait states (dummy clocks) not support 38h 04:00 0 0100b 44h (1-4-4) fast read number of mode bits (note4) 000b: mode bits not support 07:05 010b (1-4-4) fast read opcode 39h 15:08 ebh ebh (1-1-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ah 20:16 0 1000b 08h (1-1-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-1-4) fast read opcode 3bh 31:24 6bh 6bh mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 104 description comment add (h) (byte) dw add (bit) data (h/b) note1 data (h) (1-1-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not supported 3ch 04:00 0 1000b 08h (1-1-2) fast read number of mode bits 000b: mode bits not supported 07:05 000b (1-1-2) fast read opcode 3dh 15:08 3bh 3bh (1-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not supported 3eh 20:16 0 0100b 04h (1-2-2) fast read number of mode bits 000b: mode bits not supported 23:21 000b (1-2-2) fast read opcode 3fh 31:24 bbh bbh (2-2-2) fast read 0=not support 1=support 40h 00 0b feh unused 03:01 111b (4-4-4) fast read 0=not support 1=support 04 1b unused 07:05 111b unused 43h:41h 31:08 ffh ffh unused 45h:44h 15:00 ffh ffh (2-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not supported 46h 20:16 0 0000b 00h (2-2-2) fast read number of mode bits 000b: mode bits not supported 23:21 000b (2-2-2) fast read opcode 47h 31:24 ffh ffh unused 49h:48h 15:00 ffh ffh (4-4-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not supported 4ah 20:16 0 0100b 44h (4-4-4) fast read number of mode bits 000b: mode bits not supported 23:21 010b (4-4-4) fast read opcode 4bh 31:24 ebh ebh sector type 1 size sector/block size = 2^n bytes (note5) 0x00b: this sector type doesn't exist 4ch 07:00 0ch 0ch sector type 1 erase opcode 4dh 15:08 20h 20h sector type 2 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 4eh 23:16 0fh 0fh sector type 2 erase opcode 4fh 31:24 52h 52h sector type 3 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 50h 07:00 10h 10h sector type 3 erase opcode 51h 15:08 d8h d8h sector type 4 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 52h 23:16 00h 00h sector type 4 erase opcode 53h 31:24 ffh ffh mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 105 table 11. parameter table (1): macronix flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) note1 data (h) vcc supply maximum voltage 2000h=2.000v 2700h=2.700v 3600h=3.600v 61h:60h 07:00 15:08 00h 36h 00h 36h vcc supply minimum voltage 1650h=1.650v 2250h=2.250v 2350h=2.350v 2700h=2.700v 63h:62h 23:16 31:24 00h 27h 00h 27h h/w reset# pin 0=not support 1=support 65h:64h 00 1b f99dh h/w hold# pin 0=not support 1=support 01 0b deep power down mode 0=not support 1=support 02 1b s/w reset 0=not support 1=support 03 1b s/w reset opcode reset enable (66h) should be issued before reset opcode. 11:04 1001 1001b (99h) program suspend/resume 0=not support 1=support 12 1b erase suspend/resume 0=not support 1=support 13 1b unused 14 1b wrap-around read mode 0=not support 1=support 15 1b wrap-around read mode opcode 66h 23:16 c0h c0h wrap-around read data length 08h:support 8b wrap-around read 16h:8b&16b 32h:8b&16b&32b 64h:8b&16b&32b&64b 67h 31:24 64h 64h individual block lock 0=not support 1=support 6bh:68h 00 1b cb85h individual block lock bit (volatile/nonvolatile) 0=volatile 1=nonvolatile 01 0b individual block lock opcode 09:02 1110 0001b (e1h) individual block lock volatile protect bit default protect status 0=protect 1=unprotect 10 0b secured otp 0=not support 1=support 11 1b read lock 0=not support 1=support 12 0b permanent lock 0=not support 1=support 13 0b unused 15:14 11b unused 31:16 ffh ffh unused 6fh:6ch [31:00] ffh ffh mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 106 note 1: h/b is hexadecimal or binary . note 2: (x-y-z) means i/o mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). at the present time, the only valid read sfdp instruction modes are: (1-1-1), (2-2-2), and (4-4-4) note 3: wait states is required dummy clock cycles after the address bits or optional mode bits. note 4: mode bits is optional control bits that follow the address bits. these bits are driven by the system controller if they are specifed. (eg,read performance enhance toggling bits) note 5: 4kb=2^0ch,32kb=2^0fh,64kb=2^10h note 6: all unused and undefned area data is blank ffh. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 107 10. reset driving the reset# pin low for a period of trlrh or longer will reset the device. after reset cycle, the device is at the following states: - standby mode - all the volatile bits such as wel/wip/sram lock bit will return to the default status as power on. - 3-byte address mode if the device is under programming or erasing, driving the rese t# pin low will also terminate the operation and data could be lost. during the resetting cycle, the so data becomes high impedance and the current will be reduced to minimum. symbol parameter min. typ. max. unit trhsl reset# high before cs# low 10 us trs reset# setup time 15 ns trh reset# hold time 15 ns trlrh reset# low pulse width 10 us tready1 reset recovery time 35 us figure 114. reset timing trhsl trs trh trlrh tready1 / tready2 sclk reset# cs# table 12. reset timing-(power on) symbol parameter min. typ. max. unit trhsl reset# high before cs# low 10 us trs reset# setup time 15 ns trh reset# hold time 15 ns trlrh reset# low pulse width 10 us tready2 reset recovery time (during instruction decoding) 40 us reset recovery time (for read operation) 40 us reset recovery time (for program operation) 310 us reset recovery time(for se4kb operation) 12 ms reset recovery time (for be64k/be32kb operation) 25 ms reset recovery time (for chip erase operation) 1000 ms reset recovery time (for wrsr operation) 40 ms table 13. reset timing-(other operation) mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 108 11. power-on state the device is at below states when power-up: - standby mode (please n ote it is not deep power-down mode) - w rite enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power- up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. when vcc is lower than vwi (por threshold voltage value), the internal logic is reset and the fash device has no response to any command. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. please refer to the " power-up timing". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uf) - at power-down stage, the vcc drops below vwi level, all operations are disable and device has no response to any command. the data corruption might occur during the stage while a write, program, erase cycle is in progress. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 109 12. electrical specifications figure 115. maximum negative overshoot waveform figure 116. maximum positive overshoot waveform notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to vcc+2.0v or -2.0v for period up to 20ns. table 14. absolute maximum ratings rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.5v vcc to ground potential -0.5v to 4.0v table 15. capacitance ta = 25c, f = 1.0 mhz symbol parameter min. typ. max. unit conditions cin input capacitance 8 pf vin = 0v cout output capacitance 8 pf vout = 0v vss vss-2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 110 figure 117. input test waveforms and measurement level figure 118. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.8v 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test cl 25k ohm 25k ohm +3.0v cl=30pf including jig capacitance mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 111 table 16. dc characteristics (temperature = -40 c to 85 c, vcc = 2.7v ~ 3.6v) notes : 1. t ypical values at vcc = 3.3v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. t ypical value is calculated by simulation. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 50 100 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 5 20 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 20 ma f=104mhz, (4 x i/o read) sclk=0.1vcc/0.9vcc, so=open 15 ma f=84mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 20 25 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 20 ma program status register in progress, cs#=vcc icc4 vcc sector/block (32k, 64k) erase current (se/be/be32k) 1 20 25 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 20 25 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.8 v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.2 v iol = 100ua voh output high voltage vcc-0.2 v ioh = -100ua mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 112 table 17. ac characteristics (temperature = -40 c to 85 c, vcc = 2.7v ~ 3.6v) symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for all commands(except read operation) d.c. 166 mhz frsclk fr clock frequency for read instructions 66 mhz ftsclk clock frequency for fast read, dread, 2read, qread, 4read, fastdtrd, 2dtrd, 4dtrd see "dummy cycle and frequency table (mhz)" mhz tch (1) tclh clock high time others (fsclk) 45% ftsclk ns normal read (frsclk) 7 ns tcl (1) tcll clock low time others (fsclk) 45% ftsclk ns normal read (frsclk) 7 ns tclch (2) clock rise time (peak to peak) 0.1 v/ns tchcl (2) clock fall time (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 3 ns tchsl cs# not active hold time (relative to sclk) 4 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 2 ns tchsh cs# active hold time (relative to sclk) 3 ns tshch cs# not active setup time (relative to sclk) 3 ns tshsl tcsh cs# deselect time read 7 ns write/erase/program 30 ns tshqz (2) tdis output disable time 8 ns tclqv tv clock low to output valid loading: 30pf 8 ns loading: 15pf 6 ns loading: 10pf 5 ns tclqx tho output hold time 1 ns twhsl (3) write protect setup time 20 ns tshwl (3) write protect hold time 100 ns tdp (2) cs# high to deep power-down mode 10 us tres1 (2) cs# high to standby mode without electronic signature read 30 us tres2 (2) cs# high to standby mode with electronic signature read 30 us tw write status/confguration register cycle time 40 ms twreaw write extended address register 40 ns tbp byte-program 12 60 us tpp page program cycle time 0.6 3 ms tpp (5) page program cycle time (n bytes) 0.016 + 0.016* (n/16) (6) 3 ms tse sector erase cycle time 43 200 ms tbe32 block erase (32kb) cycle time 190 1000 ms tbe block erase (64kb) cycle time 340 2000 ms tce chip erase cycle time 240 600 s notes: 1. tch + tcl must be greater than or equal to 1/ frequency. 2. typical values given for ta=25 c. not 100% tested. 3. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 4. test condition is shown as figure 117 and figure 118. 5. while programming consecutive bytes, page program instruction provides optimized timings by selecting to program the whole 256 bytes or only a few bytes between 1~256 bytes. 6. n=how many bytes to program. the number of (n/16) will be round up to next integer. in the formula, while n=1, byte program time=32us. while n=17, byte program time=48us. 7. by default dummy cycle value. please refer to the "table 1. read performance comparison" . mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 113 notes : 1. sampled, not 100% tested . 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to table 17 . ac characteristics. symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v 13. operating conditions at device power-up and power-down ac timing illustrated in figure 119 and figure 120 are for the supply voltages and the control signals at device power-up and power-down. if the timing in the fgures is ignored, the device will not operate correctly . during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 119. ac timing at device power-up sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 114 figure 120. power-down sequence cs# sclk vcc during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. figure 121. power-up timing v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) v wi mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 115 13-1. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). figure 122. power up/down and voltage drop table 18. power-up/down voltage and timing vcc time vcc (max.) vcc (min.) v tpwd tvsl chip select is not allowed full device access allowed pwd (max.) for power-down to power-up operation, the vcc of fash device must below v pwd for at least tpwd timing. please check the table below for more detail. symbol parameter min. max. unit tvsl vcc(min.) to device operation 1500 us vwi command inhibit voltage 2.3 2.5 v v pwd vcc voltage needed to below v pwd for ensuring initialization will occur 0.9 v tpwd the minimum duration for ensuring initialization will occur 300 us tvr vcc rise time 20 500000 us/v vcc vcc power supply 2.7 3.6 v note: these parameters are characterized only. mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 116 14. erase and programming performance note: 1. t ypical program and erase time assumes the following conditions: 25 c, 3.3v, and checkerboard pattern. 2. under worst conditions of 85 c and 2.7v. 3. syste m-level overhead is the time required to execute the frst-bus-cycle sequence for the programming command. 4. the maximum chip programming time is evaluated under the worst conditions of 0c, vcc=3.3v, and 100k cycle with 90% confdence level. min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. parameter min. typ. (1) max. (2) unit write status register cycle time 40 ms sector erase cycle time (4kb) 43 200 ms block erase cycle time (32kb) 0.19 1 s block erase cycle time (64kb) 0.34 2 s chip erase cycle time 240 600 s byte program time (via page program command) 12 60 us page program time 0.6 3 ms erase/program cycle 100,000 cycles parameter condition min. max. unit data retention 55?c 20 years 15. data retention 16. latch-up characteristics mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 117 17. ordering information part no. clock (mhz) temperature package remark mx25l51245gmi-10g 104 -40 c~85 c 16-sop (300mil) mx25l51245gz2i-10g 104 -40 c~85 c 8-wson (8x6mm) mx25l51245g xdi-10g 104 -40 c~85 c 24-ball bga (5x5 ball array) mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 118 18. part name description mx 25 l 10 z2 i g option: g: rohs compliant & halogen-free speed: 10: 104mhz temperature range: i: industrial (-40c to 85c) package: m: 16-sop (300mil) z2: 8-wson (8x6mm) xd: 24-ball bga (5x5 ball array) density & mode: 51245g: 512mb type: l: 3v device: 25: serial flash 51245g mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 119 19. package information mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 120 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 121 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 122 20. revision history revision no. description page date 0.01 1. modifed 16-pin sop p7 jan/06/2014 2. updated parameters for ac characteristics p1 12 3. content correction p88~94,1 16 4. modifed vcc to ground potential parameter p109 5. corrected figure 42~51 p54~58 mx25l51245g rev. 0.01, jan. 06, 2014 preliminary p/n: pm2006 mx25l51245g 123 macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which has been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2013~2014. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at: http://www.macronix.com |
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